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PDF ADG715 Data sheet ( Hoja de datos )
| Número de pieza | ADG715 | |
| Descripción | CMOS/ Low Voltage Serially-Controlled/ Octal SPST Switches | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADG715 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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a CMOS, Low Voltage
Serially-Controlled, Octal SPST Switches
ADG714/ADG715
FEATURES
ADG714 SPI™/QSPI™/MICROWIRE™-Compatible Interface
ADG715 I2C™-Compatible Interface
2.7 V to 5.5 V Single Supply
؎3 V Dual Supply
2.5 ⍀ On Resistance
0.6 ⍀ On Resistance Flatness
100 pA Leakage Currents
Octal SPST
Power-On Reset
Fast Switching Times
TTL/CMOS-Compatible
Small TSSOP Package
APPLICATIONS
Data Acquisition Systems
Communication Systems
Relay Replacement
Audio and Video Switching
FUNCTIONAL BLOCK DIAGRAMS
ADG714
S1
S2
S3
S4
S5
S6
S7
S8
INPUT SHIFT
REGISTER
D1 S1
D2 S2
D3 S3
D4 S4
D5 S5
D6 S6
D7 S7
D8 S8
DOUT
ADG715
INTERFACE
LOGIC
SCLK DIN SYNC RESET
SDA SCL A0 A1
D1
D2
D3
D4
D5
D6
D7
D8
RESET
GENERAL DESCRIPTION
The ADG714/ADG715 are CMOS, octal SPST (single-pole,
single-throw) switches controlled via either a two- or 3-wire
serial interface. On resistance is closely matched between switches
and very flat over the full signal range. Each switch conducts
equally well in both directions and the input signal range extends
to the supplies. Data is written to these devices in the form of
8 bits, each bit corresponding to one channel.
The ADG714 utilizes a 3-wire serial interface that is compatible
with SPI , QSPI and MICROWIRE and most DSP interface
standards. The output of the shift register DOUT enables a
number of these parts to be daisy chained.
The ADG715 utilizes a 2-wire serial interface that is compatible
with the I2C interface standard. The ADG715 has four hard wired
addresses, selectable from two external address pins (A0 and A1).
This allows the 2 LSBs of the 7-bit slave address to be set by the
user. A maximum of four of these devices may be connected to
the bus.
On power-up of these devices, all switches are in the OFF con-
dition, and the internal registers contain all zeros.
Low power consumption and operating supply range of 2.7 V to
5.5 V make this part ideal for many applications. These parts
may also be supplied from a dual ± 3 V supply. The ADG714
and ADG715 are available in a small 24-lead TSSOP package.
PRODUCT HIGHLIGHTS
1. 2-3-Wire Serial Interface.
2. Single/Dual Supply Operation. The ADG714 and ADG715
are fully specified and guaranteed with 3 V, 5 V, and ± 3 V
supply rails.
3. Low On Resistance, typically 2.5 Ω.
4. Low Leakage.
5. Power-On Reset.
6. Small 24-lead TSSOP package.
I2C is a trademark of Philips Corporation.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
ADG714/ADG715
ADG714 TIMING CHARACTERISTICS1, 2 (VDD = 2.7 V to 5.5 V. All specifications –40؇C to +85؇C unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
Unit
Conditions/Comments
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t93
30
33
13
13
0
5
4.5
0
33
20
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Frequency
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Rising Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
SCLK Rising Edge to DOUT Valid
NOTES
1See Figure 1.
2All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3CL = 20 pF, RL = 1 kΩ.
Specifications subject to change without notice.
t1
SCLK
SYNC
DIN
DOUT
t8
t4
t6
t5
DB7
t9
DB71
DB61
t2
t3
t7
DB0
DB21 DB11 DB01
NOTE
1DATA FROM PREVIOUS WRITE CYCLE
Figure 1. 3-Wire Serial Interface Timing Diagram
REV. 0
–5–
5 Page 
0.04
0.02
0
–0.02
IS, ID (ON)
VDD = 3V
VSS = GND
TA = 25؇C
ID (OFF)
IS (OFF)
0.1
0.05
0
–0.05
ADG714/ADG715
ID, IS (ON)
VDD = 3V
VSS = GND
VD = 3V/1V
VS = 1V/3V
IS (OFF)
ID (OFF)
–0.04
0 0.5 1 1.5 2 2.5 3
VOLTAGE – V
Figure 9. Leakage Currents as a Function of VD (VS)
–0.1
10 20 30 40 50 60 70 80
TEMPERATURE – ؇C
Figure 12. Leakage Currents as a Function of Temperature
0.04
0.02
0
–0.02
IS (OFF)
VDD = +3V
VSS = –3V
TA = 25؇C
ID (OFF)
IS, ID (ON)
–0.04
–3 –2 –1 0 1 2 3
VOLTAGE – V
Figure 10. Leakage Currents as a Function of VD (VS) Dual
Supply
0
VDD = 5V
TA = 25؇C
–20
–40
–60
–80
–100
–120
30k
100k
1M 10M
FREQUENCY – Hz
100M
Figure 13. Off Isolation vs. Frequency
0.1
0.05
VDD = +3V
VSS = –3V
VD = +2.25V/–1.25V
VS = –1.25V/+2.25V
VDD = +5V
VSS = GND
VD = 4.5V/1V
VS = 1V/4.5V
IS, ID (ON)
0
–0.05
ID (OFF)
IS (OFF)
–0.1
10 20 30 40 50 60 70 80
TEMPERATURE – ؇C
Figure 11. Leakage Currents as Function of Temperature
0
–2
–4
–6
–8
–10
–12
–14
30k 100k
1M 10M
FREQUENCY – Hz
100M 300M
Figure 14. On Response vs. Frequency
REV. 0
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADG715.PDF ] | |
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