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PDF ADG465 Data sheet ( Hoja de datos )
| Número de pieza | ADG465 | |
| Descripción | Single Channel Protector in an SOT-23 Package | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Fault and Overvoltage Protection up to ؎40␣ V
Signal Paths Open Circuit with Power Off
Signal Path Resistance of RON with Power On
44 V Supply Maximum Ratings
Low On Resistance 80 ⍀ Typ
1 nA Max Path Current Leakage @ +25؇C
Low Power Dissipation 0.8␣ W Typ
Latchup-Proof Construction
APPLICATIONS
ATE Equipment
Sensitive Measurement Equipment
Hot-Insertion Rack Systems
ADC Input Channel Protection
Single Channel Protector
in an SOT-23 Package
ADG465
FUNCTIONAL BLOCK DIAGRAM
VDD VSS
VIN
VIN
VDD
VD1
VS1
VOUT
ADG465
VOUT
VDD
OUTPUT CLAMPED
@ VDD – 1.5V
GENERAL DESCRIPTION
The ADG465 is a single channel protector in an SOT-23 pack-
age. The channel protector is placed in series with the signal
path, and will protect sensitive components from voltage tran-
sience in the signal path whether or not the power supplies are
present. Because the channel protection works regardless of the
presence of the supplies, the channel protectors are ideal for use
in applications where correct power sequencing cannot always
be guaranteed to protect analog inputs (e.g., hot-insertion rack
systems). This is discussed further, and some example circuits
are given, in the Applications section of this data sheet.
A channel protector consists of an n-channel MOSFET, a
p-channel MOSFET and an n-channel MOSFET, connected in
series. The channel protector behaves like a series resistor dur-
ing normal operation, i.e., (VSS + 2 V) < VIN < (VDD – 1.5 V).
When a channel’s analog input exceeds the power supplies
(including VDD and VSS = 0 V), one of the MOSFETs will
switch off, clamping the output to either VSS + 2 V or VDD – 1.5 V.
Circuitry and signal source protection is provided in the event of
an overvoltage or power loss. The channel protectors can with-
stand overvoltage inputs from –40 V to +40 V. See the Circuit
Information section of this data sheet.
The ADG465 can operate from both bipolar and unipolar
supplies. The channels are normally on when power is con-
nected, and open circuit when power is disconnected. With
power supplies of ± 15 V, the on-resistance of the ADG465 is
80 Ω typ, with a leakage current of ± 1 nA max. When power
is disconnected, the input leakage current is approximately
± 5 nA typ.
The ADG465 is available in a 6-lead plastic surface mount
SOT-23 package, and an 8-lead µSOIC package.
PRODUCT HIGHLIGHTS
1. Fault Protection.
The ADG465 can withstand continuous voltage inputs from
–40 V to +40 V. When a fault occurs due to the power sup-
plies being turned off, or due to an overvoltage being applied
to the ADG465, the output is clamped. When power is turned
off, current is limited to the nanoampere level.
2. Low Power Dissipation.
3. Low RON 80 Ω typ.
4. Trench Isolation Latchup-Proof Construction.
A dielectric trench separates the p- and n-channel MOSFETs
thereby preventing latchup.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
1 page  
ADG465
CIRCUIT INFORMATION
Figure 6 below shows a simplified schematic of a channel pro-
tector circuit. The circuit is comprised of four MOS transis-
tors—two NMOS and two PMOS. One of the PMOS devices
does not lie directly in the signal path, but is used to connect the
source of the second PMOS device to its backgate. This has the
effect of lowering the threshold voltage and increasing the
input signal range of the channel for normal operation. The
source and backgate of the NMOS devices are connected for the
same reason. During normal operation the channel protectors
have a resistance of 80␣ Ω typ. The channel protectors are very
low power devices; even under fault conditions the supply cur-
rent is limited to sub-microampere levels. All transistors are
dielectrically isolated from each other using a trench isolation
method. This makes it impossible to latch up the channel pro-
tectors. For an explanation, see Trench Isolation section.
VSS
VSS – VTP where VTP is the threshold voltage of the PMOS
device (2␣ V typ). If the input voltage exceeds these threshold
voltages, the output of the channel protector (no load) is
clamped at these threshold voltages. However, the channel
protector output will clamp at a voltage inside these thresholds
if the output is loaded. For example, with an output load of
1␣ kΩ, VDD = 15␣ V and a positive overvoltage. The output will
clamp at VDD – VTN – ∆V = 15␣ V – 1.5␣ V – 0.6␣ V = 12.9␣ V
where ∆V is due to I. R voltage drops across the channels of the
MOS devices (see Figure 8). As can be seen from Figure 8, the
current during fault condition is determined by the load on the
output (i.e., VCLAMP/RL). However, if the supplies are off, the
fault current is limited to the nanoampere level.
Figures 7, 9 and 10 show the operating conditions of the signal
path transistors during various fault conditions. Figure 7 shows
how the channel protectors operate when a positive overvoltage
is applied to the channel protector.
VDD – VTN*
(+13.5V)
NMOS
PMOS
NMOS
VDD
PMOS
VSS
VDD
Figure 6. The Channel Protector Circuit
Overvoltage Protection
When a fault condition occurs on the input of a channel pro-
tector, the voltage on the input has exceeded some threshold
voltage set by the supply rail voltages. The threshold voltages
are related to the supply rails as follows: for a positive overvolt-
age, the threshold voltage is given by VDD – VT where VTN is the
threshold voltage of the NMOS transistor (1.5␣ V typ). In the
case of a negative overvoltage the threshold voltage is given by
POSITIVE
OVERVOLTAGE
(+20V)
NMOS
PMOS
SATURATED
NON-
SATURATED
VDD (+15V)
VSS (–15V)
*VTN = NMOS THRESHOLD VOLTAGE (+1.5V)
NMOS
NON-
SATURATED
VDD (+15V)
Figure 7. Positive Overvoltage on the Channel Protector
The first NMOS transistor goes into a saturated mode of opera-
tion as the voltage on its Drain exceeds the Gate voltage (VDD) –
the threshold voltage (VTN). This situation is shown in Figure 8.
The potential at the source of the NMOS device is equal to VDD
–VTN. The other MOS devices are in a nonsaturated mode of
operation.
VD
(+20V)
VG
(VDD = +15V)
VS
(+13.5V)
OVERVOLTAGE
OPERATION
(SATURATED)
N+
EFFECTIVE
SPACE CHARGE
REGION
VT = 1.5V
P–
N+ N+
N-CHANNEL
(VG – VT = 13.5V)
⌬V
PMOS
NMOS
NONSATURATED
OPERATION
IOUT
RL VCLAMP
Figure 8. Positive Overvoltage Operation on the Channel Protector
REV. A
–5–
5 Page | ||
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| PDF Descargar | [ Datasheet ADG465.PDF ] | |
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