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PDF ADG3245 Data sheet ( Hoja de datos )
| Número de pieza | ADG3245 | |
| Descripción | 2.5 V/3.3 V / 8-Bit 2-Port Level Translating / Bus Switch | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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2.5 V/3.3 V, 8-Bit, 2-Port
Level Translating, Bus Switch
ADG3245
FEATURES
225 ps Propagation Delay through the Switch
4.5 ⍀ Switch Connection between Ports
Data Rate 1.244 Gbps
2.5 V/3.3 V Supply Operation
Selectable Level Shifting/Translation
Level Translation
3.3 V to 2.5 V
3.3 V to 1.8 V
2.5 V to 1.8 V
Small Signal Bandwidth 610 MHz
20-Lead TSSOP and LFCSP Packages
APPLICATIONS
3.3 V to 1.8 V Voltage Translation
3.3 V to 2.5 V Voltage Translation
2.5 V to 1.8 V Voltage Translation
Bus Switching
Bus Isolation
Hot Swap
Hot Plug
Analog Switch Applications
GENERAL DESCRIPTION
The ADG3245 is a 2.5 V or 3.3 V, 8-bit, 2-port digital switch.
It is designed on Analog Devices’ low voltage CMOS process,
which provides low power dissipation yet gives high switching
speed and very low on resistance, allowing inputs to be connected
to outputs without additional propagation delay or generating
additional ground bounce noise.
The switches are enabled by means of the bus enable (BE) input
signal. These digital switches allow bidirectional signals to be
switched when ON. In the OFF condition, signal levels up to
the supplies are blocked.
This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from 3.3 V
inputs to 2.5 V outputs is allowed. Similarly, if the device is
operated from a 2.5 V supply and 2.5 V inputs are applied, the
device will translate the outputs to 1.8 V. In addition to this, a
level translating select pin (SEL) is included. When SEL is low,
VCC is reduced internally, allowing for level translation between
3.3 V inputs and 1.8 V outputs. This makes the device suited to
applications requiring level translation between different supplies,
such as converter to DSP/microcontroller interfacing.
FUNCTIONAL BLOCK DIAGRAM
A0 B0
A7 B7
BE
PRODUCT HIGHLIGHTS
1. 3.3 V or 2.5 V supply operation
2. Extremely low propagation delay through switch
3. 4.5 W switches connect inputs to outputs
4. Level/voltage translation
5. 20-lead TSSOP and LFCSP (4 mm ¥ 4 mm) packages
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADG3245
TERMINOLOGY
VCC
GND
VINH
VINL
II
IOZ
IOL
VP
RON
⌬RON
CX OFF
CX ON
CIN
ICC
⌬ICC
tPLH, tPHL
tPZH, tPZL
tPHZ, tPLZ
Max Data Rate
Channel Jitter
fBE
Positive Power Supply Voltage.
Ground (0 V) Reference.
Minimum Input Voltage for Logic 1.
Maximum Input Voltage for Logic 0.
Input Leakage Current at the Control Inputs.
OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.
ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.
Maximum Pass Voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device
when the switch input voltage is equal to the supply voltage.
Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified
amount of current through the switch.
On Resistance Match between Any Two Channels, i.e., RON Max – RON Min.
OFF Switch Capacitance.
ON Switch Capacitance.
Control Input Capacitance. This consists of BE and SEL.
Quiescent Power Supply Current. This current represents the leakage current between the VCC and ground pins.
It is measured when all control inputs are at a logic HIGH or LOW level and the switches are OFF.
Extra power supply current component for the BE control input when the input is not driven at the supplies.
Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant
RON ¥ CL, where CL is the load capacitance.
Bus Enable Times. These are the times taken to cross the VT voltage at the switch output when the switch turns on
in response to the control signal, BE.
Bus Disable Times. This is the time taken to place the switch in the high impedance OFF state in response to the control
signal. It is measured as the time taken for the output voltage to change by V⌬ from the original quiescent level,
with reference to the logic level transition at the control input. (Refer to Figure 3 for enable and disable times.)
Maximum Rate at which Data Can Be Passed through the Switch.
Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel.
Operating Frequency of Bus Enable. This is the maximum frequency at which bus enable (BE) can be toggled.
–4– REV.$
5 Page 
ADG3245
VOUT
1.8V
3.3V SUPPLY
SEL = 0V
CPU
PLUG-IN
CARD (1)
CARD I/O
VIN
0V SWITCH 3.3V
INPUT
Figure 10. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V
Bus Isolation
A common requirement of bus architectures is low capacitance
loading of the bus. Such systems require bus bridge devices that
extend the number of loads on the bus without exceeding the
specifications. Because the ADG3245 is designed specifically for
applications that do not need drive yet require simple logic
functions, it solves this requirement. The device isolates access
to the bus, thus minimizing capacitance loading.
LOAD A
LOAD C
BUS/
BACKPLANE
BUS SWITCH
LOCATION
LOAD B
LOAD D
Figure 11. Location of Bus Switched in a Bus
Isolation Application
Hot Plug and Hot Swap Isolation
The ADG3245 is suitable for hot swap and hot plug applications.
The output signal of the ADG3245 is limited to a voltage that is
below the VCC supply, as shown in Figures 6, 8, and 10. Therefore
the switch acts like a buffer to take the impact from hot insertion,
protecting vital and expensive chipsets from damage.
In hot-plug applications, the system cannot be shutdown when
new hardware is being added. To overcome this, a bus switch can
be positioned on the backplane between the bus devices and the
hot plug connectors. The bus switch is turned off during hot plug.
Figure 12 shows a typical example of this type of application.
RAM
PLUG-IN
CARD (2)
CARD I/O
Figure 12. ADG3245 in a Hot Plug Application
There are many systems that require the ability to handle hot
swapping, such as docking stations, PCI boards for servers, and
line cards for telecommunications switches. If the bus can be
isolated prior to insertion or removal, then there is more control
over the hot swap event. This isolation can be achieved using a
bus switch. The bus switches are positioned on the hot swap card
between the connector and the devices. During hot swap, the
ground pin of the hot swap card must connect to the ground pin
of the back plane before any other signal or power pins.
Analog Switching
Bus switches can be used in many analog switching applications;
for example, video graphics. Bus switches can have lower on
resistance, smaller ON and OFF channel capacitance and thus
improved frequency performance than their analog counterparts.
The bus switch channel itself consisting solely of an NMOS
switch limits the operating voltage (see TPC 1 for a typical
plot), but in many cases, this does not present an issue.
High Impedance During Power-Up/Power-Down
To ensure the high impedance state during power-up or power-
down, BE should be tied to VCC through a pull-up resistor; the
minimum value of the resistor is determined by the current-
sinking capability of the driver.
PACKAGE AND PINOUT
The ADG3245 is packaged in both a small 20-lead TSSOP or a
tiny 20-lead LFCSP package. The area of the TSSOP option is
37.5 mm2, while the area of the LFCSP option is 16 mm2. This
leads to a 57% savings in board space when using the LFCSP pack-
age compared with the TSSOP package. This makes the LFCSP
option an excellent choice for space-constrained applications.
The ADG3245 in the TSSOP package offers a flowthrough
pinout. The term flowthrough signifies that all the inputs are on
opposite sides from the outputs. A flowthrough pinout simplifies
the PCB layout.
–10–
REV.$
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ADG3245.PDF ] | |
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