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Analog Devices - Fractional-N Frequency Synthesizer

Numéro de référence ADF4153
Description Fractional-N Frequency Synthesizer
Fabricant Analog Devices 
Logo Analog Devices 





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ADF4153 fiche technique
Data Sheet
Fractional-N Frequency Synthesizer
ADF4153
FEATURES
GENERAL DESCRIPTION
RF bandwidth to 4 GHz
2.7 V to 3.3 V power supply
Separate VP allows extended tuning voltage
Y version available: −40°C to +125°C
Programmable fractional modulus
Programmable charge pump currents
3-wire serial interface
Analog and digital lock detect
Power-down mode
Pin-compatible with ADF4110/ADF4111/ADF4112/ADF4113
and ADF4106
Consistent RF output phase
Loop filter design possible with ADIsimPLL
Qualified for automotive applications
APPLICATIONS
CATV equipment
Base stations for mobile radio (GSM, PCS, DCS, WiMAX,
SuperCell 3G, CDMA, W-CDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA)
Wireless LANs, PMR
Communications test equipment
The ADF4153 is a fractional-N frequency synthesizer
that implements local oscillators in the upconversion
and downconversion sections of wireless receivers and
transmitters. It consists of a low noise digital phase
frequency detector (PFD), a precision charge pump, and
a programmable reference divider. There is a Σ-Δ based
fractional interpolator to allow programmable fractional-N
division. The INT, FRAC, and MOD registers define an
overall N divider (N = (INT + (FRAC/MOD))). In addition,
the 4-bit reference counter (R counter) allows selectable
REFIN frequencies at the PFD input. A complete phase-
locked loop (PLL) can be implemented if the synthesizer is
used with an external loop filter and a voltage controlled
oscillator (VCO).
A simple 3-wire interface controls all on-chip registers.
The device operates with a power supply ranging from
2.7 V to 3.3 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD VP SDVDD
RSET
ADF4153
REFIN
MUXOUT
×2
DOUBLER
4-BIT
R COUNTER
HIGH-Z
OUTPUT
MUX
VDD
DGND
VDD
RDIV
NDIV
LOCK
DETECT
THIRD ORDER
FRACTIONAL
INTERPOLATOR
REFERENCE
+ PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
CURRENT
SETTING
RFCP3 RFCP2 RFCP1
N-COUNTER
RFINA
RFINB
CLK
DATA
LE
24-BIT
DATA
REGISTER
FRACTION MODULUS
REG
REG
INTEGER
REG
AGND
DGND
Figure 1.
CPGND
Rev. F
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

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