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PDF ADC674AJP Data sheet ( Hoja de datos )
| Número de pieza | ADC674AJP | |
| Descripción | Microprocessor-Compatible ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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® ADC674A
Microprocessor-Compatible
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q COMPLETE 12-BIT A/D CONVERTER
WITH REFERENCE, CLOCK, AND 8-, 12-,
OR 16-BIT MICROPROCESSOR BUS
INTERFACE
q IMPROVED PERFORMANCE SECOND
SOURCE FOR ADC574A/674A-TYPE A/D
CONVERTERS
Conversion Time: 15µs max
Bus Access Time:150ns max
A0 Input: Bus Contention During Read
Operation Eliminated
q FULLY SPECIFIED FOR OPERATION ON
±12V OR ±15V SUPPLIES
q NO MISSING CODES OVER
TEMPERATURE:
0°C to +75°C ADC674AJH, KH, JP, KP
Grades
–55°C to +125°C (ADC674ASH, TH Grades)
DESCRIPTION
The ADC674A is a 12-bit successive approximation
analog-to-digital converter, utilizing state-of-the-art
CMOS and laser-trimmed bipolar die custom-designed
for freedom from latch-up and for optimum AC per-
formance. It is complete with a self-contained +10V
reference, internal clock, digital interface for micro-
processor control, and three-state outputs.
The reference circuit, containing a buried zener, is
laser-trimmed for minimum temperature coefficient.
The clock oscillator is current-controlled for excel-
lent stability over temperature. Full-scale and offset
errors may be externally trimmed to zero. Internal
scaling resistors are provided for the selection of
analog input signal ranges of 0V to +10V, 0V to
+20V, ±5V, and ±10V.
The converter may be externally programmed to
provide 8- or 12-bit resolution. The conversion time
for 12 bits is factory set for 15µs maximum.
Output data are available in a parallel format from
TTL-compatible three-state output buffers. Output data
are coded in straight binary for unipolar input signals
and bipolar offset binary for bipolar input signals.
The ADC674A, available in both industrial and
military temperature ranges, requires supply voltages
of +5V and ±12V or ±15V. It is packaged in a 28-pin
plastic DIP, or hermetic side-brazed ceramic DIP.
Control
Inputs
Control
Logic
Status
Bipolar
Offset
20V Range
10V Range
Reference
Input
Reference
Output
Clock
Comparator
12-Bit D/A
Converter
10V
Reference
Parallel
Data
Output
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1984 Burr-Brown Corporation
PDS-551D
Printed in U.S.A. October, 1993
1 page  
STAND-ALONE OPERATION
For stand-alone operation, control of the converter is accom-
plished by a single control line connected to R/C. In this
mode CS and AO are connected to digital common and CE
and 12/8 are connected to VLOGIC (+5V). The output data are
presented as 12-bit words. The stand-alone mode is used in
systems containing dedicated input ports which do not
require full bus interface capability.
Conversion is initiated by a high-to-low transition of R/C.
The three-state data output buffers are enabled when R/C is
high and STATUS is low. Thus, there are two possible
modes of operation; conversion can be initiated with either
positive or negative pulses. In either case, the R/C pulse
must remain low for a minimum of 50ns.
Figure 1 illustrates timing when conversion is initiated by an
R/C pulse which goes low and returns to the high state
during the conversion. In this case, the three-state outputs go
to the high-impedance state in response to the falling edge of
R/C and are enabled for external access of the data after
completion of the conversion. Figure 2 illustrates the timing
when conversion is initiated by a positive R/C pulse. In this
mode, the output data from the previous conversion is
enabled during the positive portion of R/C. A new conver-
sion is started on the falling edge of R/C, and the three-state
outputs return to the high impedance state until the next
occurrence of a high R/C pulse. Timing specifications for
stand-alone operation are listed in Table III.
tHRL
R/C
tDS
STATUS
DB11-DB0
tHDR
Data Valid
tC
High-Z State
tHS
Data Valid
FIGURE 1. R/C Pulse Low—Outputs Enabled After Con-
versions.
R/C
tHRH
tDS
STATUS
tDDR
High-Z
DB11-DB0
tHDR
Data Valid
tC
High-Z State
FIGURE 2. R/C Pulse High—Outputs Enabled Only While
R/C is High.
SYMBOL
PARAMETER
tHRL Low R/C Pulse Width
tDS STS Delay from R/C
tHDR Data Valid After R/C Low
tHS STS Delay After Data Valid
tHRH High R/C Pulse Width
tDDR Data Access Time
MIN
50
25
300
150
TYP
400
TABLE III. Stand-Alone Mode Timing.
MAX UNITS
200
1000
150
ns
ns
ns
ns
ns
ns
FULLY CONTROLLED OPERATION
Conversion Length
Conversion length (8-bit or 12-bit) is determined by the state
of the AO input, which is latched upon receipt of a conver-
sion start transition (described below). If AO is latched high,
the conversion continues for 8 bits. The full 12-bit conver-
sion will occur if AO is low. If all 12 bits are read following
an 8-bit conversion the 3LSBs (DB0 - DB2) will be low
(logic 0) and DB3 will be high (logic 1). AO
is latched because it is also involved in enabling the output
buffers. No other control inputs are latched.
CONVERSION START
The converter is commanded to initiate conversion by a
transition occurring on any of three logic inputs (CE, CS,
and R/C) as shown in Table II. Conversion is initiated by the
last of the three to reach the required state and thus all three
may be dynamically controlled. If necessary, all three may
change states simultaneously, and the nominal delay time is
the same regardless of which input actually starts conver-
sion. If it is desired that a particular input establish the actual
start of conversion, the other two should be stable a mini-
mum of 50ns prior to the transition of that input. Timing
relationships for start of conversion timing are illustrated in
Figure 3. The specifications for timing are contained in
Table IV.
CE
tSSC
CS
R/C
tSRC
AO
tSAC
STATUS
DB11-DB0
tHEC
tHSC
tHRC
tHAC
tDSC
tC
High Impedance
FIGURE 3. Conversion Cycle Timing.
5 ADC674A
®
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