ADC16471 Datasheet PDF - National Semiconductor
| Part Number | ADC16471 | |
| Description | 16-Bit Delta-Sigma 192 ks/s Analog-to-Digital Converters | |
| Manufacturers | National Semiconductor | |
| Logo |  |
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February 1995
ADC16071 ADC16471
16-Bit Delta-Sigma 192 ks s Analog-to-Digital Converters
General Description
The ADC16071 ADC16471 are 16-bit delta-sigma analog-
to-digital converters using 64 c oversampling at
12 288 MHz A 5th-order comb filter and a 246 tap FIR deci-
mation filter are used to achieve an output data rate of up to
192 kHz The combination of oversampling and internal digi-
tal filtering greatly reduces the external anti-alias filter re-
quirements to a simple RC low pass filter The FIR filters
offer linear phase response 0 005 dB passband ripple and
t90 dB stopband rejection The ADC16071 ADC16471’s
analog fourth-order modulator uses switched capacitor
technology A built-in fully-differential bandgap voltage ref-
erence is also included in the ADC16471 The ADC16071
has no internal reference and requires externally applied
reference voltages
The ADC16071 ADC16471 use an advanced BiCMOS pro-
cess for a low power consumption of 500 mW (max) while
operating from a single 5V supply A power-down mode re-
duces the power supply current from 100 mA (max) in the
active mode to 1 3 mA (max)
The ADC16071 ADC16471 are ideal analog-to-digital front
ends for signal processing applications They provide a
complete high resolution signal acquisition system that re-
quires a minimal external anti-aliasing filter reference or
interface logic
The ADC16071 ADC16471’s serial interface is compatible
with the DSP56001 TMS320 and ADSP2100 digital signal
processors
Key Specifications
Y Resolution
Y Total harmonic distortion
48 kHz output data rate
192 kHz output data rate
Y Maximum output data rate
Y Power dissipation
Active
192 kHz output data rate
48 kHz output data rate
Power-down
16 bits
b94 dB (typ)
b80 dB (typ)
192 kHz (min)
500 mW (max)
275 mW (max)
6 5 mW (max)
Key Features
Y Voltage reference (ADC16471 only)
Y Fourth-order modulator
Y 64 c oversampling with a 12 288 MHz sample rate
Y Adjustable output data rate from 7 kHz to 192 kHz
Y Linear-phase digital anti-aliasing filter
0 005 dB passband ripple
90 dB stopband rejection
Y Single a5V supply
Y Power-down mode
Y Serial data interface compatible with popular
DSP devices
Applications
Y Medical instrumentation
Y Process control systems
Y Test equipment
Y High sample-rate audio
Y Digital Signal Processing (DSP) analog front-end
Y Vibration and noise analysis
Connection Diagram
Ordering Information
Part No
Package
ADC16471CIN
ADC16471CIWM
ADC16071CIN
ADC16071CIWM
24-Pin Molded DIP
24-Pin SOIC
24-Pin Molded DIP
24-Pin SOIC
NS Package
No
N24C
M24B
N24C
M24B
TL H 11454 – 2
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL H 11454
RRD-B30M75 Printed in U S A
|
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DC Electrical Characteristics
The following specifications apply for VAa e VDa e VMa e 5V unless otherwise specified Boldface limits apply for TA
e TJ e TMIN to TMAX all other limits TA e TJ e 25 C
Symbol
Parameter
Conditions
Typical Limits
(Note 6) (Note 7)
Units
(Limit)
VIH Logic High Input Voltage
VDa e 5 25V
VDa
23
V (max)
V (min)
VIL Logic Low Input Voltage
VDa e 4 75V
08
b0 3
V (max)
V (min)
VOH
VOL
IIN(1)
IIN(0)
ITSI
CIN
Logic High Output Voltage
Logic Low Output Voltage
Logical ‘‘1’’ Input Current
Logical ‘‘0’’ Input Current
SDO TRI-STATE Leakage Current
Logic Input Capacitance
Logic High Output Current e b400 mA
VDa e 4 75V
Logic Low Output Current e 2 mA
VDa e 5 25V
VIN e 0 4V to 2 4V
VIN e 0 to VDa
10
b1 0
10
5
2 4 V (min)
05
50
b5 0
50
V (max)
mA (max)
mA (max)
mA (max)
pF
AC Electrical Characteristics for Clock In (CLK) Serial Clock Out (SCO) and
Frame Sync In (FSI)
The following specifications apply for VAa e VDa e VMa e 5V unless otherwise specified Boldface limits apply for TA
e TJ e TMIN to TMAX all other limits TA e TJ e 25 C
Symbol
Parameter
Conditions
Typical
(Note 6)
Limits
(Note 7)
Units
(Limit)
fCLK
tCLK
tCLKL
tCLKH
tR
CLK Frequency Range
(fCLK e 1 tCLK)
CLK Period
(tCLK e 1 fCLK)
CLK Low Pulse Width
CLK High Pulse Width
CLK Rise Time
25
1
1000
40
16
14
10
3
MHz (max)
MHz (min)
ns (max)
ns (min)
ns (min)
ns (min)
ns (max)
ns (min)
tF CLK Fall Time
10 ns (max)
3 ns (min)
tFSILOW
Minimum Frame Sync Input
Low Time before Frame Sync
Input Asserted High
2 tCLK (min)
tFSISU
tFSIH
tSCOD
Frame Sync Input Setup Time
Frame Sync Input Hold Time
Serial Clock Output Delay
Time from Rising Edge
of CLK
10 ns (min)
10 ns (min)
12
20 ns (max)
5 ns (min)
tSCO
Serial Clock Output Period
4 tCLK
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for ADC16471 electronic component. |
| Information | Total 20 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ ADC16471.PDF Datasheet ] | |
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Featured Datasheets
| Part Number | Description | MFRS |
| ADC16471 | The function is 16-Bit Delta-Sigma 192 ks/s Analog-to-Digital Converters. National Semiconductor | |
| ADC16471CIN | The function is 16-Bit Delta-Sigma 192 ks/s Analog-to-Digital Converters. National Semiconductor | |
| ADC16471CIWM | The function is 16-Bit Delta-Sigma 192 ks/s Analog-to-Digital Converters. National Semiconductor | |
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