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PDF ADC14071CIVBH Data sheet ( Hoja de datos )
| Número de pieza | ADC14071CIVBH | |
| Descripción | 14-Bit/ 7 MSPS/ 380 mW A/D Converter | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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November 1999
ADC14071
14-Bit, 7 MSPS, 380 mW A/D Converter
General Description
The ADC14071 is a 14-bit, monotholic analog to digital con-
verter capable of conversion rates up to 8 Megasamples per
second. This CMOS converter uses a differential, piperlined
architecture with digital error correction and an on-chip
track-and-hold circuit to maintain superb dynamic perfor-
mance with input frequencies up to 20MHz. Tested and guar-
anteed dynamic performance specifications provide the de-
signer with known performance. The ADC14071 operates on
a +5V single supply consuming just 380mW (typical). The
Power Down feature reduces power consumption to 20mW,
typical.
The differential inputs provide a full scale input swing of
±VREF with the possibility of a single input. Full use of the dif-
ferential input is recommended for optimum perfomance. For
ease of use, the reference input is single ended. This single-
ended reference input is converted on-chip to a differential
reference configuration for use by the processing circuitry.
Output data format is 14-bit straight binary.
The ADC14071 may be used to replace many hybrid con-
verters with a resultant saving of space, power and cost.
The ADC14071 comes in a 48-pin TQFP and is specified to
operate over the industrial temperature range of −40˚C to
+85˚C.
Features
n Single +5V Operation
n Power Down Mode
n TTL/CMOS Input/Output Compatible
Key Specifications
n Resolution
n Max Conversion Rate
n DNL
n SNR (fIN = 500 kHz)
n ENOB (fW = 500 kHz)
n Supply Voltage
n Power Consumption
Applications
n Document Scanners
n Imaging
n Instrumentation
n PC-Based Data Acquisition
n Spectrum Analyzers
n Sonar/Radar
n xDSL
n Wireless Local Loop
n Data Acquisition Systems
n DSP Front End
Connection Diagram
14 Bits
7 Msps (min)
±0.6 LSB (typ)
80 dB (typ)
12.6 Bits (typ)
+5V ±5%
380 mW (typ)
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS101101
DS101101-1
www.national.com
1 page  
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
(V+ = VA = VD = DR VD)
VA − DR VD, VD − DR VD
Voltage on Any I/O Pin
Input Current at Pins 1, 45 and
47(Note 3)
Input Current at Any Other Pin (Note
3)
6.0V
≥0V
−0.5V to V+ +0.5V
±10 mA
±25 mA
Package Input Current (Note 3)
Power Dissipation at TA = 25˚C
ESD Susceptibility (Note 5)
Human Body Model
Machine Model
±50 mA
See (Note 4)
1500V
200V
Soldering Temperature, Infrared,
10 seconds (Note 6)
Storage Temperature
300˚C
−65˚C to +150˚C
Operating Ratings (Notes 1, 2)
Operating Temperature Range
VA, VD
DR VD
VREF
Digital Inputs
Analog Inputs
|VA − VD|
|AGND − DGND|
−40˚C ≤ TA ≤ +85˚C
+4.75V to +5.25V
2.7V to VD
1.0V to 2.7V
−0.3V to VD + 0.3V
−0.3V to VA + 0.3V
≤100 mV
0V to 100 mV
Converter Electrical Characteristics
The following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +5.0VDC, DR VD = 3.0V or 5.0V, PD = 0V,
aVpREpFlyINfo=r+T2A.0=V,TVJIN=
(common mode) = 1.0V, fCLK
TMIN to TMAX: all other limits
= 7 MHz @ 50% duty cycle,
TA = TJ = 25˚C (Notes 7, 8,
tr, tr
9)
=
4ns,
CL
=
20
pF/pin.
Boldface
limits
Symbol
Parameter
Conditions
Typical
Limits
(Note 10) (Note 11)
Units
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
14 Bits (min)
INL Integral Non-Linearity (note 12)
±2.2
LSB
DNL Differential Non-Linearity
±0.6
+1.0
−0.85
LSB (max)
FSE Positive and Negative Full-Scale
Error
25˚C
0.9 2.3
%FS
TC FSE Full-Scale Error Tempco
−5 ppm/˚C
ZSE Zero Offset Error
25˚C
0.1 %FS
TC ZSE Zero Offset Error Tempco
−0.6 ppm/˚C
REFERENCE AND ANALOG INPUT CHARACTERISTICS
VREF Reference Voltage Range
2.00
1.0
2.7
V(min)
V(max)
RR Reference Input Resistance
CR Reference Input Capacitance
VIN Input Voltage Range (VIN+ − VIN−) VIN (common Mode) = VREF/2
10M
5
±2.0
±1.0
±2.7
Ohms
pF
V(min)
V(max)
CIN VIN+, VIN− Input Capacitance
(CLK LOW)
VIN = 1.0V+0.7 Vrms (CLK HIGH)
14
5
pF
pF
DYNAMIC CONVERTER CHARACTERISTICS
BW Full Power Bandwidth
−1 dB
−3 dB
20 MHz
25 MHz
ENOB Effective Number of Bits
SINAD Signal-to-Noise and Distortion
SNR Signal -to-Noise Ratio (Note 13)
THD Total Harmonic Distortion
fIN = 500 kHz
fIN = 3.5 MHz
fIN = 500 kHz
fIN = 3.5 MHz
fIN = 500 kHz
fIN = 3.5 MHz
fIN = 500 kHz
fIN = 3.5 MHz
12.6
12.0 Bits (min)
12.0
Bits
77 74 dB (min)
74 dB
80 78 dB (min)
77 dB
−83 −76 dB (min)
−79 dB
5 www.national.com
5 Page 
Specification Definitions (Continued)
Distortion or SINAD. ENOB is defined as (SINAD -
1.76)/6.02 and says that the converter is equivalent to a per-
fect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input. The test
is performed with fIN equal to 100 kHz plus integer multiples
of fCLK. The input frequency at which the output is −3 dB
relative to the low frequency input signal is the full power
bandwidth.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the intermodulation
products to the total power in the original frequencies. IMD is
usually expressed in dB.
INTEGRAL NON-LINEARITY (INL) is a measure of the de-
viation of each individual code from a line drawn from nega-
tive full scale (1⁄2 LSB below the first code transition) through
positive full scale (the last code transition). The deviation of
any given code from this straight line is measured from the
center of that code value.
NEGATIVE FULL SCALE ERROR is the measure of how far
the last code transition is from the ideal of 1⁄2LSB above
nominal negative full scale. It is the difference between the
input voltage (VIN+ − VIN−) just causing a transition to the first
code and the ideal voltage to cause that transition. The ideal
LSB transition (when it should occur) is (VIN+) − (VIN−) =
1⁄2LSB
OFFSET ERROR is the difference between the ideal and ac-
tual voltages that cause a transition to mid-scale (a code of
8192) when approached from a lower code. The ideal LSB
transition (when it should occur) is (VIN+) − (VIN−) = 0
Timing Diagram
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and the availability of that
same conversion result at the output. New data is available
at every clock cycle, but the data lags the conversion by the
pipeline delay.
POSITIVE FULL SCALE ERROR is a measure of how far
the last code transition is from the ideal of 11⁄2LSB below
nominal positive full scale. It is the difference beween the in-
put voltage (VIN+ − VIN−) just causing a transition to positive
full scale and VREF − 11⁄2LSB. Full Scalse Error is sometimes
called Full Scale Offset Error.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or dc.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD)
is the ratio, expressed in dB, of the rms value of the input sig-
nal to the rms value of all of the other spectral components
below half the clock frequency, including harmonics but ex-
cluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not
present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-
pressed in dB or dBc, of the rms total of the first nine har-
monic components to the rms value of the input signal.
Output Timing
11
DS101101-23
www.national.com
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