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PDF ADC12D040EVAL Data sheet ( Hoja de datos )
| Número de pieza | ADC12D040EVAL | |
| Descripción | Dual 12-Bit/ 40 MSPS/ 600 mW A/D Converter with Internal/External Reference and Sample-and-Hold | |
| Fabricantes | National Semiconductor | |
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December 2002
ADC12D040
Dual 12-Bit, 40 MSPS, 600 mW A/D Converter with
Internal/External Reference and Sample-and-Hold
General Description
The ADC12D040 is a dual, low power monolithic CMOS
analog-to-digital converter capable of converting analog in-
put signals into 12-bit digital words at 40 Megasamples per
second (MSPS), minimum. This converter uses a differential,
pipelined architecture with digital error correction and an
on-chip sample-and-hold circuit to minimize die size and
power consumption while providing excellent dynamic per-
formance. Operating on a single 5V power supply, the
ADC12D040 achieves 10.9 effective bits at 10 MHz input
and consumes just 600 mW at 40 MSPS, including the
reference current. The Power Down feature reduces power
consumption to 75 mW.
The differential inputs provide a full scale input swing equal
to VREF with the possibility of a single-ended input. Full use
of the differential input is recommended for optimum perfor-
mance. For ease of use, the buffered, high impedance,
single-ended reference input is converted on-chip to a differ-
ential reference for use by the processing circuitry. The
digital outputs for the two ADCs are available on separate
12-bit buses with an output data format choice of offset
binary or 2’s complement.
For ease of interface, the digital output driver power pins of
the ADC12D040 can be connected to a separate supply
voltage in the range of 2.5V to the digital supply voltage,
making the outputs compatible with low voltage systems.
When not converting, power consumption can be reduced by
pulling the PD pin high, placing the converter into the power-
down state where it typically consumes just 75 mW. The
ADC12D040’s speed, resolution and single supply operation
make it well suited for a variety of applications.
This device is available in the 64-lead TQFP package and
will operate over the industrial temperature range of −40˚C to
+85˚C.
Features
n Binary/2’s comp output format
n Single supply operation
n Internal sample-and-hold
n Outputs 2.5V to 5V compatible
n TTL/CMOS compatible input/outputs
n Low power consumption
n Power down mode
n On-chip reference buffer
n Internal/External 2V reference
Key Specifications
n Resolution
n Conversion Rate
n DNL
n INL
n SNR (fIN = 10MHz)
n ENOB (fIN = 10MHz)
n THD (fIN = 10 MHz)
n SFDR (fIN = 10 MHz)
n Data Latency
n Supply Voltage
n Power Consumption, Operating
n Power Down
n Crosstalk
Applications
n Ultrasound and Imaging
n Instrumentation
n Communications Receivers
n Sonar/Radar
n xDSL
n Cable Modems
n DSP Front Ends
12 Bits
40 MSPS(min)
±0.4 LSB(typ)
±0.7 LSB(typ)
68 dB(typ)
10.9 bits(typ)
−78 dB (typ)
80 dB (typ)
6 Clock Cycles
+5V ±5%
600 mW(typ)
75 mW(typ)
80 dB(typ)
© 2002 National Semiconductor Corporation DS200460
www.national.com
1 page  
Pin Descriptions and Equivalent Circuits (Continued)
Pin No.
Symbol
Equivalent Circuit
Description
24–29
34–39
DA0–DA11
42–47
52–57
DB0–DB11
Digital data output pins that make up the 12-bit conversion
results of their respective converters. DA0 and DB0 are the
LSBs, while DA11 and DB11 are the MSBs of the output
word. Output levels are TTL/CMOS compatible.
ANALOG POWER
9, 18, 19,
62, 63
VA
3, 8, 10,
17, 20, 61,
64
AGND
DIGITAL POWER
33, 48
32, 49
VD
DGND
30, 51
VDR
23, 31, 40,
50, 58
DR GND
Positive analog supply pins. These pins should be connected
to a quiet +5V source and bypassed to AGND with 0.1 µF
monolithic capacitors located within 1 cm of these power pins,
and with a 10 µF capacitor.
The ground return for the analog supply.
Positive digital supply pin. This pin should be connected to
the same quiet +5V source as is VA and be bypassed to
DGND with a 0.1 µF monolithic capacitor located within 1 cm
of the power pin and with a 10 µF capacitor.
The ground return for the digital supply.
Positive digital supply pins for the ADC12D040’s output
drivers. These pins should be connected to a voltage source
of +2.5V to +5V and bypassed to DR GND with a 0.1 µF
monolithic capacitor. If the supply for these pins are different
from the supply used for VA and VD, they should also be
bypassed with a 10 µF tantalum capacitor. VDR should never
exceed the voltage on VD. All bypass capacitors should be
located within 1 cm of the supply pin.
The ground return for the digital supply for the ADC12D040’s
output drivers. These pins should be connected to the system
digital ground, but not be connected in close proximity to the
ADC12D040’s DGND or AGND pins. See Section 5 (Layout
and Grounding) for more details.
5 www.national.com
5 Page 
Timing Diagram
Transfer Characteristic
Output Timing
20046009
20046010
FIGURE 1. Transfer Characteristic
11 www.national.com
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet ADC12D040EVAL.PDF ] | |
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