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PDF ADC12451883 Data sheet ( Hoja de datos )
| Número de pieza | ADC12451883 | |
| Descripción | Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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December 1994
ADC12451 Dynamically-Tested Self-Calibrating
12-Bit Plus Sign A D Converter with Sample-and-Hold
General Description
The ADC12451 is a CMOS 12-bit plus sign successive ap-
proximation analog-to-digital converter whose dynamic
specifications (S N THD etc ) are tested and guaranteed
On request the ADC12451 goes through a self-calibration
cycle that adjusts linearity zero and full-scale errors The
ADC12451 also has the ability to go through an Auto-Zero
cycle that corrects the zero error during every conversion
The analog input to the ADC12451 is tracked and held by
the internal circuitry so an external sample-and-hold is not
required The ADC12451 has a S H control input which di-
rectly controls the track-and-hold state of the A D A unipo-
lar analog input voltage range (0V to a5V) or a bipolar
range (b5V to a5V) can be accommodated with g5V sup-
plies
The 13-bit data result is available on the eight outputs of the
ADC12451 in two bytes high-byte first and sign extended
The digital inputs and outputs are compatible with TTL or
CMOS logic levels
Applications
Y Digital Signal Processing
Y Audio
Y Telecommunications
Y High Resolution Process Control
Y Instrumentation
Features
Y Self-calibration provides excellent temperature stability
Y Internal sample-and-hold
Y 8-bit mP DSP interface
Y Bipolar input range with a single a5V reference
Key Specifications
Y Resolution
Y Conversion Time
Y Sampling Rate
Y Bipolar Signal Noise
Y Total Harmonic Distortion
Y Aperture Time
Y Aperture Jitter
Y Zero Error
Y Positive Full-Scale Error
Y Power Consumption g5V
12 bits plus sign
7 7 ms (max)
83 kHz (max)
73 5 dB (min)
b78 0 dB (max)
100 ns
100 psrms
g2 LSB (max)
g1 5 LSB (max)
113 mW (max)
Simplified Block Diagram
Connection Diagram
Dual-In-Line Package
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL H 11025
Top View
TL H 11025 – 2
TL H 11025 – 1
Ordering Information
Industrial
(b40 C s TA s 85 C)
ADC12451CIJ
Package
J24A
Military
(b55 C s TA s 125 C)
Package
ADC12451CMJ
ADC12451CMJ 883
J24A
RRD-B30M115 Printed in U S A
1 page  
AC Electrical Characteristics (Continued)
The following specifications apply for DVCC e AVCC e a5 0V Vb e b5 0V tr e tf e 20 ns unless otherwise specified
Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C (Notes 6 and 7)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limit
(Note 10 19)
Units
(Limit)
tA Acquisition Time
(Note 15)
RSOURCE e 50X
35
3 5 ms(min)
tIA Internal Acquisition Time
(when using WR Control Only)
7(1 fCLK)
7(1 fCLK)
(max)
tZA Auto Zero Time a
Acquisition Time
tD(EOC)L Delay from Hold Command
to Falling Edge of EOC
fCLK e 1 75 MHz
Using WR Control
Using S H Control
33(1 fCLK)
18 8
200
100
33(1 fCLK) a 250 ns
19 05
350
150
(max)
ms(max)
ns(max)
ns(max)
tCAL
Calibration Time
tW(CAL)L
tW(WR)L
tACC
Calibration Pulse Width
minimum WR Pulse Width
maximum Access Time
(Delay from Falling Edge of
RD to Output Data Valid)
fCLK e 3 5 MHz
(Note 16)
CL e 100 pF
1399 (1 fCLK)
399
60
60
50
1399 (1 fCLK)
400
200
200
95
(max)
ms(max)
ns(min)
ns(min)
ns(max)
t0H t1H
TRI-STATE Control (Delay
from Rising Edge of RD
to Hi-Z State)
RL e 1 kX
CL e 100 pF
30
70 ns(max)
tPD(INT)
maximum Delay from Falling Edge
of RD or WR to Reset of INT
100
175
ns(max)
tRR Delay between Successive RD Pulses
30 60 ns(min)
Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is
functional but do not guarantee specific performance limits For guaranteed specifications and test conditions see the Electrical Characteristics The guaranteed
specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test
conditions
Note 2 All voltages are measured with respect to AGND and DGND unless otherwise specified
Note 3 When the input voltage (VIN) at any pin exceeds the power supply rails (VIN k Vb or VIN l (AVCC or DVCC) the current at that pin should be limited to
5 mA The 20 mA maximum package input current rating allows the voltage at any four pins with an input current limit of 5 mA to simultaneously exceed the power
supply voltages
Note 4 The power dissipation of this device under normal operation should never exceed 191 mW (Quiescent Power Dissipation a 1 TTL Load on each digital
output) Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition (ex when any inputs or
outputs exceed the power supply) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMax (maximum junction
temperature) iJA (package junction to ambient thermal resistance) and TA (ambient temperature) The maximum allowable power dissipation at any temperature
is PDMax e (TJMax b TA) iJA or the number given in the Absolute Maximum Ratings whichever is lower For this device TJMax e 150 C and the typical thermal
resistance (iJA) of the ADC12451 with CMJ and CIJ suffixes when board mounted is 51 C W
Note 5 Human body model 100 pF discharged through a 1 5 kX resistor
Note 6 Two on-chip diodes are tied to the analog input as shown below Errors in the A D conversion can occur if these diodes are forward biased more than
50 mV This means that if AVCC and DVCC are minimum (4 75 VDC) and Vb is maximum (b4 75 VDC) the analog input full-scale voltage must be s g4 8 VDC
TL H 11025 – 4
5
5 Page 
Timing Diagrams (Continued)
Using WR Control to Start a Conversion without Auto-Zero (CAL 1 AZ e 1)
Using S H Control to Start a Conversion without Auto-Zero (AZ e 1 CAL e 1)
TL H 11025 – 18
TL H 11025 – 19
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ADC12451883.PDF ] | |
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