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PDF ADC1241CMJ Data sheet ( Hoja de datos )
| Número de pieza | ADC1241CMJ | |
| Descripción | Self-Calibrating 12-Bit Plus Sign mP-Compatible A/D Converter with Sample-and-Hold | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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November 1994
ADC1241 Self-Calibrating 12-Bit Plus
Sign mP-Compatible A D Converter
with Sample-and-Hold
General Description
The ADC1241 is a CMOS 12-bit plus sign successive ap-
proximation analog-to-digital converter On request the
ADC1241 goes through a self-calibration cycle that adjusts
positive linearity and full-scale errors to less than g LSB
each and zero error to less than g1 LSB The ADC1241
also has the ability to go through an Auto-Zero cycle that
corrects the zero error during every conversion
The analog input to the ADC1241 is tracked and held by the
internal circuitry and therefore does not require an external
sample-and-hold A unipolar analog input voltage range (0V
to a5V) or a bipolar range (b5V to a5V) can be accom-
modated with g5V supplies
The 13-bit word on the outputs of the ADC1241 gives a 2’s
complement representation of negative numbers The digi-
tal inputs and outputs are compatible with TTL or CMOS
logic levels
Applications
Y Digital Signal Processing
Y High Resolution Process Control
Y Instrumentation
Key Specifications
Y Resolution
Y Conversion Time
Y Linearity Error
g
Y Zero Error
Y Positive Full Scale Error
Y Power Consumption
12 Bits plus Sign
13 8ms (max)
LSB (g0 0122%) (max)
g1LSB (max)
g1LSB (max)
70mW (max)
Features
Y Self-calibrating
Y Internal sample-and-hold
Y Bipolar input range with g5V supplies and single
a5V reference
Y No missing codes over temperature
Y TTL MOS input output compatible
Y Standard 28-pin DIP
TRI-STATE is a registered trademark of National Semiconductor Corporation
Simplified Schematic
Connection Diagram
Dual-In-Line Package
C1995 National Semiconductor Corporation TL H 10554
Top View
TL H 10554 – 2
Order Number ADC1241CMJ
ADC1241CMJ 883 ADC1241BIJ or
ADC1241CIJ
See NS Package Number J28A
TL H 10554 – 1
RRD-B30M115 Printed in U S A
1 page  
AC Electrical Characteristics (Continued)
Note 7 A diode exists between AVCC and DVCC as shown below
TL H 10554 – 4
To guarantee accuracy it is required that the AVCC and DVCC be connected together to a power supply with separate bypass filters at each VCC pin
Note 8 Accuracy is guaranteed at fCLK e 2 0 MHz At higher and lower clock frequencies accuracy may degrade See curves in the Typical Performance
Characteristics Section
Note 9 Typicals are at TJ e 25 C and represent most likely parametric norm
Note 10 Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level)
Note 11 Positive linearity error is defined as the deviation of the analog value expressed in LSBs from the straight line that passes through positive full scale and
zero For negative linearity error the straight line passes through negative full scale and zero (See Figures 1b and 1c )
Note 12 The ADC1241’s self-calibration technique ensures linearity full scale and offset errors as specified but noise inherent in the self-calibration process will
result in a repeatability uncertainty of g0 20 LSB
Note 13 If TA changes then an Auto-Zero or Auto-Cal cycle will have to be re-started see the typical performance characteristic curves
Note 14 After an Auto-Zero or Auto-Cal cycle at the specified power supply extremes
Note 15 If the clock is asynchronous to the falling edge of WR an uncertainty of one clock period will exist in the interval of tA therefore making the minimum tA e
6 clock periods and the maximum tA e 7 clock periods If the falling edge of the clock is synchronous to the rising edge of WR then tA will be exactly 6 5 clock
periods
Note 16 The CAL line must be high before any other conversion is started
Note 17 The specifications for these parameters are valid after an Auto-Cal cycle has been completed
Note 18 A military RETS electrical test specification is available on request At time of printing the ADC1241CMJ 883 RETS specification complies fully with the
boldface limits in this column
FIGURE 1a Transfer Characteristic
5
TL H 10554 – 5
5 Page 
2 0 Functional Description (Continued)
Digital Control Inputs
CS WR RD CAL AZ
A D Function
1
1
1
1
1XX
0X1
1 1 Start Conversion without Auto-Zero
1 1 Read Conversion Result without Auto-Zero
1 0 Start Conversion with Auto-Zero
1 0 Read Conversion Result with Auto-Zero
X Start Calibration Cycle
0 X Test Mode (DB2 DB3 DB5 and DB6 become active)
FIGURE 1 Function of the A D Control Inputs
The table in Figure 1 summarizes the effect of the digital
control inputs on the function of the ADC1241 The Test
Mode where RD is high and CS and CAL are low is used by
the factory to thoroughly check out the operation of the
ADC1241 Care should be taken not to inadvertently be in
this mode since DB2 DB3 DB5 and DB6 become active
outputs which may cause data bus contention
2 2 RESETTING THE A D
All internal logic can be reset which will abort any conver-
sion in process The A D is reset whenever a new conver-
sion is started by taking CS and WR low If this is done when
the analog input is being sampled or when EOC is low the
Auto-Cal correction factors may be corrupted therefore
making it necessary to do an Auto-Cal cycle before the next
conversion This is true with or without Auto-Zero The Cali-
bration Cycle cannot be reset once started On power-up
the ADC1241 automatically goes through a Calibration Cy-
cle that takes typically 1396 clock cycles
3 0 Analog Considerations
3 1 REFERENCE VOLTAGE
The voltage applied to the reference input of the converter
defines the voltage span of the analog input (the difference
between VIN and AGND) over which 4095 positive output
codes and 4096 negative output codes exist The A-to-D
can be used in either ratiometric or absolute reference ap-
plications The voltage source driving VREF must have a
very low output impedance and very low noise The circuit in
Figure 2 is an example of a very stable reference that is
appropriate for use with the ADC1241
In a ratiometric system the analog input voltage is propor-
tional to the voltage used for the A D reference When this
voltage is the system power supply the VREF pin can be
tied to VCC This technique relaxes the stability requirement
of the system reference as the analog input and A D refer-
ence move together maintaining the same output code for
given input condition
Tantalum
FIGURE 2 Low Drift Extremely Stable Reference Circuit
TL H 10554 – 17
11
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