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PDF ADC12281CIVT Data sheet ( Hoja de datos )
| Número de pieza | ADC12281CIVT | |
| Descripción | 12-Bit/ 20 MSPS Single-Ended Input/ Pipelined A/D Converter | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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March 2000
ADC12281
12-Bit, 20 MSPS Single-Ended Input, Pipelined A/D
Converter
General Description
The ADC12281 is a monolithic CMOS analog-to-digital con-
verter capable of converting analog input signals into 12-bit
digital words at 20 megasamples per second (MSPS). It uti-
lizes a pipeline architecture to minimize die size and power
dissipation. Self-calibration and error correction maintain ac-
curacy and performance over temperature.
The ADC12281 operates on a 5V power supply and can digi-
tize single-ended analog input signals in the range of 0V to
2V. A single convert clock controls the conversion operation
and all digital I/O is TTL compatible.
The ADC12881 is designed to minimize external compo-
nents necessary for the analog input interface. An internal
sample-and-hold circuit samples the single-ended analog in-
put and an internal amplifier buffers the reference voltage in-
put.
The Power Down feature reduces power consumption to
20 mW, typical.
The ADC12281 is available in the 32-lead TQFP package
and is designed to operate over the industrial temperature
range of −40˚C to +85˚C.
Features
n Single 5V power supply
n Single-ended analog input
n Internal sample-and-hold
n Internal reference buffer amplifier
n Low offset and gain errors
Key Specifications
n Resolution
n Conversion rate
n DNL
n SNR
n ENOB
n Analog input range
n Supply voltage
n Power consumption, 20 MHz
Applications
n Digital signal processing front end
n Digital television
n Radar
n High speed data links
n Waveform digitizers
n Quadrature demodulation
12 bits
up to 20 MSPS
0.35 LSB (typ)
65.5 dB (typ)
10.5 bits (typ)
2 VPP (min)
+5V ±5%
443 mW (typ)
Connection Diagram
DS101027-1
32-Lead TQFP Package
Order Number ADC12281CIVT
See NS Package Number VBE32A
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS101027
www.national.com
1 page  
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltages (VA, VD, VD I/O)
|VA–VD|
VD I/O–VA, VD I/O–VD
Voltage on Any Input or Output Pin
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation at TA = 25˚C
6.5V
≤100 mV
≤300 mV
−0.3V to VA +0.3V
±25 mA
±50 mA
See (Note 4)
ESD Susceptibility
Human Body Model (Note 5)
Machine Model (Note 5)
Soldering Temperature, Infrared,
(10 sec.) (Note 6)
Storage Temperature
2500V
250V
300˚C
−65˚C to +150˚C
Operating Ratings (Notes 1, 2)
Operating Temperature Range
−40˚C ≤ TA ≤ +85˚C
Supply Voltage (VA, VD)
+4.75V to +5.25V
Output Driver Supply Voltage (VD I/O)
+2.7V to VD
VREF Input
1.8V to 2.2V
CLOCK, CAL, PD, OE
−0.05V to VD +0.05V
Ground Difference |AGND–DGND|
≤100 mV
Converter Electrical Characteristics
The following specifications apply for AGND = DGND = DGND I/O = 0V, VA = VD = VD I/O = +5V, PD = +5V, VREF = +2.0V,
fCLK = 20 MHz, 3 VP-P at 50% duty cycle, CL = 25 pF/pin. After Auto-Cal. Boldface limits apply for TA = TJ = TMIN to TMAX;
all other limits TA = TJ = 25˚C (Notes 7, 8, 9).
Symbol
Parameter
Conditions
Typical
Limits
(Note 10) (Note 11)
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
12 Bits (min)
INL Integral Non-Linearity
±1.0
±2.5
LSB (max)
DNL
Differential Non-Linearity
±0.35
±0.9
LSB (max)
Full-Scale Error
+3 ±10 LSB (max)
Zero Error
+7 ±17 LSB (max)
DYNAMIC CONVERTER CHARACTERISTICS
BW Full Power Bandwidth
100 MHz
SNR
Signal-to-Noise Ratio
fIN = 4.43 MHz, VIN = 2.0 VP-P
SINAD
Signal-to-Noise and Distortion
fIN = 4.43 MHz, VIN = 2.0 VP-P
ENOB
Effective Number of Bits
fIN = 4.43 MHz, VIN = 2.0 VP-P
THD
Total Harmonic Distortion
fIN = 4.43 MHz, VIN = 2.0 VP-P
SFDR
Spurious Free Dynamic Range
fIN = 4.43 MHz, VIN = 2.0 VP-P
REFERENCE AND ANALOG INPUT CHARACTERISTICS
65.5
65
10.5
−76
75
62.5
62
10
dB (min)
dB (min)
Bits (min)
dB
dB
VIN Input Voltage Range
CIN VIN Input Capacitance
(CLK LOW)
VREF
V (max)
10 pF
(CLK HIGH)
15
pF
VREF
Reference Voltage (Note 14)
1.8 V (min)
2.00
2.2 V (max)
Reference Input Leakage Current
10 µA
Reference Input Resistance
1 MΩ
DC and Logic Electrical Characteristics
The following specifications apply for AGND = DGND = DGND I/O = 0V, VA = VD = VD I/O = +5V, PD = +5V, VREF = +2.0V,
fCLK = 20 MHz, 3 VP-P at 50% duty cycle, CL = 25 pF/pin. After Auto-Cal. Boldface limits apply for TA = TJ = TMIN to TMAX;
all other limits TA = TJ = 25˚C (Notes 7, 8, 9).
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limits)
CLOCK, CAL, PD, OE DIGITAL INPUT CHARACTERISTICS
VIH Logical “1” Input Voltage
VIL Logical “0” Input Voltage
IIH Logical “1” Input Current
IIL Logical “0” Input Current
CIN Logic Input Capacitance
VD = 5.25V
VD = 4.75V
VIN = 5.0V
VIN = 0V
2.0 V (min)
0.8 V (max)
10 µA
−10 µA
8 pF
5 www.national.com
5 Page 
Typical Performance Characteristics (VA = VD = VD I/O = 5V, fCLK = 20 MHz, unless otherwise
stated) (Continued)
THD vs Temperature
Spectral Response @ 20 MSPS
DS101027-26
Specification Definitions
CONVERSION LATENCY: See PIPELINE DELAY.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion or SINAD. ENOB is defined as (SINAD -
1.76)/6.02.
FULL SCALE ERROR is the difference between the input
voltage (VIN+–VIN−) just causing a transition to positive full
scale and VREF −1.5 LSB, where VREF is (VREF+ IN) –
(VREF− IN).
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input. The test
is performed with fIN equal to 100 kHz plus integer multiples
of fCLK. The input frequency at which the output is −3 dB
relative to the low frequency input signal is the full power
bandwidth.
INTEGRAL NON-LINEARITY (INL) is a measure of the de-
viation of each individual code from a line drawn from nega-
tive full scale (1⁄2 LSB below the first code transition) through
positive full scale (the last code transition). The deviation of
any given code from this straight line is measured from the
center of that code value.
OFFSET ERROR is the difference between the ideal LSB
transition to the actual transition point. The LSB transition
should occur when VIN+ = VIN−.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and the availability of that
same conversion result at the output. New data is available
at every clock cycle, but the data lags the conversion by the
pipeline delay.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or dc.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD)
is the ratio, expressed in dB, of the rms value of the input sig-
nal to the rms value of all of the other spectral components
below half the clock frequency, including harmonics but ex-
cluding dc.
DS101027-27
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not
present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-
pressed in dB or dBc, of the rms total of the first six harmonic
components to the rms value of the input signal.
ZERO ERROR is the difference between the ideal input volt-
age (1⁄2 LSB) and the actual input voltage that just causes a
transition from an output code of zero to an output code of
one.
11 www.national.com
11 Page | ||
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| PDF Descargar | [ Datasheet ADC12281CIVT.PDF ] | |
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