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PDF ADC12062EVAL Data sheet ( Hoja de datos )
| Número de pieza | ADC12062EVAL | |
| Descripción | 12-Bit/ 1.4 MHz/ 300 mW A/D Converter with Input Multiplexer and Sample/Hold | |
| Fabricantes | National Semiconductor | |
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December 1994
ADC12062
12-Bit 1 MHz 75 mW A D Converter
with Input Multiplexer and Sample Hold
General Description
Using an innovative multistep conversion technique the
12-bit ADC12062 CMOS analog-to-digital converter digitizes
signals at a 1 MHz sampling rate while consuming a maxi-
mum of only 75 mW on a single a5V supply The
ADC12062 performs a 12-bit conversion in three lower-res-
olution ‘‘flash’’ conversions yielding a fast A D without the
cost and power dissipation associated with true flash ap-
proaches
The analog input voltage to the ADC12062 is tracked and
held by an internal sampling circuit allowing high frequency
input signals to be accurately digitized without the need for
an external sample-and-hold circuit The multiplexer output
is available to the user in order to perform additional exter-
nal signal processing before the signal is digitized
When the converter is not digitizing signals it can be placed
in the Standby mode typical power consumption in this
mode is 100 mW
Block Diagram
Features
Y Built-in sample-and-hold
Y Single a5V supply
Y Single channel or 2 channel multiplexer operation
Y Low Power Standby mode
Key Specifications
Y Sampling rate
Y Conversion time
Y Signal-to-Noise Ratio fIN e 100 kHz
Y Power dissipation (fs e 1 MHz)
Y No missing codes over temperature
1 MHz (min)
740 ns (typ)
69 5 dB (min)
75 mW (max)
Guaranteed
Applications
Y Digital signal processor front ends
Y Instrumentation
Y Disk drives
Y Mobile telecommunications
Y Waveform digitizers
Ordering Information
Industrial (b40 C s TA s a85 )
ADC12062BIV
ADC12062BIVF
ADC12062CIV
ADC12062CIVF
ADC12062EVAL
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL H 11490
Package
V44 Plastic Leaded Chip Carrier
VGZ44A Plastic Quad Flat Package
V44 Plastic Leaded Chip Carrier
VGZ44A Plastic Quad Flat Package
Evaluation Board
TL H 11490 – 1
RRD-B30M75 Printed in U S A
1 page  
Note 5 Human body model 100 pF discharged through a 1 5 kX resistor Machine model ESD rating is 200V
Note 6 See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or the section titled ‘‘Surface Mount’’ found in a current National
Semiconductor Linear Data Book for other methods of soldering surface mount devices
Note 7 Typicals are at a25 C and represent most likely parametric norm
Note 8 Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level)
Note 9 Integral Linearity Error is the maximum deviation from a straight line between the measured offset and full scale endpoints
Note 10 Dynamic testing of the ADC12062 is done using the ADC IN input The input multiplexer adds harmonic distortion at high frequencies See the graph in the
Typical Performance Characteristics section for a typical graph of THD performance vs input frequency with and without the input multiplexer
Note 11 The signal-to-noise ratio is the ratio of the signal amplitude to the background noise level Harmonics of the input signal are not included in its calculation
Note 12 The contributions from the first nine harmonics are used in the calculation of the THD
Note 13 Effective Number of Bits (ENOB) is calculated from the measured signal-to-noise plus distortion ratio (SINAD) using the equation ENOB e (SINAD b
1 76) 6 02
Note 14 The digital power supply current takes up to 10 seconds to decay to its final value after PD is pulled low This prohibits production testing of the standby
current Some parts may exhibit significantly higher standby currents than the 20 mA typical
Note 15 Power Supply Sensitivity is defined as the change in the Offset Error or the Full Scale Error due to a change in the supply voltage
TRI-STATE Test Circuit and Waveforms
TL H 11490 – 2
TL H 11490 – 4
TL H 11490 – 3
TL H 11490 – 5
5
5 Page 
Functional Description (Continued)
tap points between ( )VREF and ( )VREF This overlap of
( )VREF will automatically cancel a Voltage Estimator er-
ror of up to 256 LSBs If the first flash conversion deter-
mines that the input voltage is between ( )VREF and
(( )VREF b LSB 2) the Voltage Estimator’s output code
will be corrected by subtracting ‘‘1’’ resulting in a corrected
value of ‘‘01’’ for the first two MSBs If the first flash conver-
sion determines that the input voltage is between ( )VREF
b LSB 2) and ( )VREF the voltage estimator’s output
code is unchanged
The results of the first flash and the Voltage Estimator’s
output are given to the factory-programmed on-chip
EEPROM which returns a correction code corresponding to
the error of the MSB ladder at that tap This code is convert-
ed to a voltage by the Correction DAC To generate the next
four bits SW1 is moved to position 2 so the ladder voltage
and the correction voltage are subtracted from the input
voltage The remainder is applied to the sixteen flash con-
verters and compared with the 16 tap points from the LSB
ladder
The result of this second conversion is accurate to 10 bits
and describes the input remainder as a voltage between two
tap points (VH and VL) on the LSB ladder To resolve the
last two bits the voltage across the ladder resistor (between
VH and VL) is divided up into 4 equal parts by the capacitive
voltage divider shown in Figure 5 The divider also creates
6 LSBs below VL and 6 LSBs above VH to provide overlap
used by the digital error correction SW1 is moved to posi-
tion 3 and the remainder is compared with these 16 new
voltages The output is combined with the results of the
Voltage Estimator first flash and second flash to yield the
final 12-bit result
By using the same sixteen comparators for all three flash
conversions the number of comparators needed by the
multi-step converter is significantly reduced when compared
to standard multi-step techniques
Applications Information
1 0 MODES OF OPERATION
The ADC12062 has two interface modes An interrupt read
mode and a high speed mode Figures 1 and 2 show the
timing diagrams for these interfaces
In order to clearly show the relationship between S H CS
RD and OE the control logic decoding section of the
ADC12062 is shown in Figure 6
Interrupt Interface
As shown in Figure 1 the falling edge of S H holds the input
voltage and initiates a conversion At the end of the conver-
sion the EOC output goes high and the INT output goes
low indicating that the conversion results are latched and
may be read by pulling RD low The falling edge of RD re-
sets the INT line Note that CS must be low to enable S H
or RD
High Speed Interface
This is the fastest interface shown in Figure 2 Here the
output data is always present on the databus and the INT to
RD delay is eliminated
FIGURE 5 The Capacitive Voltage Divider
TL H 11490 – 15
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| PDF Descargar | [ Datasheet ADC12062EVAL.PDF ] | |
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| Número de pieza | Descripción | Fabricantes |
| ADC12062EVAL | 12-Bit/ 1 MHz/ 75 mW A/D Converter | National Semiconductor |
| ADC12062EVAL | 12-Bit/ 1.4 MHz/ 300 mW A/D Converter with Input Multiplexer and Sample/Hold | National Semiconductor |
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