|
|
PDF ADC10662 Data sheet ( Hoja de datos )
| Número de pieza | ADC10662 | |
| Descripción | 10-Bit 360 ns A/D Converter with Input Multiplexer and Sample/Hold | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ADC10662 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
|
No Preview Available !
June 1999
ADC10662/ADC10664
10-Bit 360 ns A/D Converter with Input Multiplexer and
Sample/Hold
General Description
Using an innovative, patented multistep* conversion tech-
nique, the 10-bit ADC10662 and ADC10664 are 2- and
4-input CMOS analog-to-digital converters offering
sub-microsecond conversion times yet dissipating a maxi-
mum of only 235 mW. The ADC10662 and ADC10664 per-
form a 10-bit conversion in two lower-resolution “flashes”,
thus yielding a fast A/D without the cost, power dissipation,
and other problems associated with true flash approaches.
In addition to standard static performance specifications
(Linearity, Full-Scale Error, etc.) dynamic performance (THD,
S/N) is guaranteed.
The analog input voltage to the ADC10662 and ADC10664 is
sampled and held by an internal sampling circuit. Input sig-
nals at frequencies from dc to over 250 kHz can therefore be
digitized accurately without the need for an external
sample-and-hold circuit.
The ADC10662 and ADC10664 include a “speed-up” pin.
Connecting an external resistor between this pin and ground
reduces the typical conversion time to as little as 360 ns.
For ease of interface to microprocessors, the ADC10662 and
ADC10664 have been designed to appear as a memory lo-
cation or I/O port without the need for external interface
logic.
Features
n Built-in sample-and-hold
n Single +5V supply
n 2- or 4-input multiplexer options
n No external clock required
Key Specifications
n Conversion time to 10 bits: 360 ns typical, 466 ns
max over temperature
n Sampling Rate: 1.5 MHz (min)
n Low power dissipation: 235 mW (max)
n Total harmonic distortion (50 kHz): −60 dB (max)
n No missing codes over temperature
Applications
n Digital signal processor front ends
n Instrumentation
n Disk drives
n Mobile telecommunications
Ordering Information
ADC10662
Industrial
(−40˚C ≤ TA ≤ +85˚C)
ADC10662CIWM
Package
M24B Small Outline
ADC10664
Industrial
(−40˚C ≤ TA ≤ +85˚C)
ADC10664CIWM
Package
M28B Small Outline
*U.S. Patent Number 4918449
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS011192
www.national.com
1 page  
DC Electrical Characteristics
The following specifications apply for V+ = +5V, VREF(+) = 5V VREF(−) = GND, and Speed Adjust pin connected to ground
through a 14.0 kΩ resistor (Mode 1) or an 8.26 kΩ resistor (Mode 2) unless otherwise specified. Boldface limits apply for
TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25˚C.
Symbol
Parameter
Conditions
Typical
(Note 7)
Limit
(Note 8)
Units
(Limits)
VIN(1)
VIN(0)
IIN(1)
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Input Current
V+ = 5.5V
V+ = 4.5V
VIN(1) = 5V
0.005
2.0 V (min)
0.8 V (max)
3.0 µA (max)
IIN(0)
VOUT(1)
VOUT(0)
IOUT
Logical “0” Input Current
Logical “1” Output Voltage
Logical “0” Output Voltage
TRI-STATE® Output Current
VIN(0) 0V
V+ = 4.5V, IOUT = −360 µA
V+ = 4.5V, IOUT = −10 µA
V+ = 4.5V, IOUT = 1.6 mA
VOUT = 5V
−0.005
0.1
−3.0
µA (max)
2.4 V (min)
4.25 V (min)
0.4 V (max)
50 µA (max)
DICC
AICC
DVCC Supply Current
AVCC Supply Current
VOUT = 0V
CS = S /H = RD = 0
CS = S /H = RD = 0
−0.1
1.0
30
−50 µA (max)
2 mA (max)
45 mA (max)
AC Electrical Characteristics
The following specifications apply for V+ = +5V, tr = tf = 20 ns, VREF(+) = 5V, VREF(−) = GND, and Speed Adjust pin con-
nected to ground through a 14.0 kΩ resistor (Mode 1) or an 8.26 kΩ resistor (Mode 2) unless otherwise specified. Boldface
limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25˚C.
Symbol
Parameter
Conditions
Typical
(Note 7)
Limit
(Note 8)
Units
(Limits)
tCONV
Mode 1 Conversion Time
from Rising Edge of S /H
to Falling Edge of INT
360 466 ns (max)
tCRD
tACC1
Mode 2 Conversion Time
Access Time (Delay from Falling
Edge of RD to Output Valid)
Mode 1; CL = 100 pF
470 610 ns (max)
30 50 ns (max)
tACC2
Access Time (Delay from Falling
Edge of RD to Output Valid)
Mode 2; CL = 100 pF
475 616 ns (max)
tSH
t1H, t0H
Minimum Sample Time
TRI-STATE Control (Delay
from Rising Edge of RD
to High-Z State)
Mode 1 (Figure 1 ) ; (Note 9)
RL = 1k, CL = 10 pF
150 ns (max)
30 60 ns (max)
tINTH
Delay from Rising Edge of RD
to Rising Edge of INT
CL = 100 pF
25 50 ns (max)
Delay from End of Conversion
tP to Next Conversion
50 ns (max)
tMS
tMH
CVIN
COUT
CIN
Multiplexer Control Setup Time
Multiplexer Hold Time
Analog Input Capacitance
Logic Output Capacitance
Logic Input Capacitance
10 75 ns (max)
10 40 ns (max)
35 pF (max)
5 pF (max)
5 pF (max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed
test conditons.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND or VIN > V+) the absolute value of current at that pin should be limited
to 5 mA or less. The 20 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD = (TJMAX − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. In most cases,
the maximum derated power dissipation will be reached only during fault conditions. For these devices, TJMAX for a board-mounted device can be found from the
tables below:
5 www.national.com
5 Page 
Applications Information (Continued)
DS011192-13
FIGURE 4. Typical Connection. Note the multiple bypass capacitors on the reference and power supply pins. If VREF−
is not grounded, it should also be bypassed to analog ground using multiple capacitors (see 5.0 “Power Supply
Considerations”). AGND and DGND should be at the same potential. VIN0 is shown with an input protection network.
4.0 INHERENT SAMPLE-AND-HOLD
Because the ADC10662 and ADC10664 sample the input
signal once during each conversion, they are capable of
measuring relatively fast input signals without the help of an
external sample-hold. In a non-sampling
successive-approximation A/D converter, regardless of
speed, the input signal must be stable to better than ±1/2
LSB during each conversion cycle or significant errors will
result. Consequently, even for many relatively slow input sig-
nals, the signals must be externally sampled and held con-
stant during each conversion if a SAR with no internal
sample-and-hold is used.
Because they incorporate a direct sample/hold control input,
the ADC10662 and ADC10664 are suitable for use in
DSP-based systems. The S /H input allows synchronization
of the A/D converter to the DSP system’s sampling rate and
to other ADC10662s, and ADC10664s.
The ADC10662 and ADC10664 can perform accurate con-
versions of input signals with frequency components from
DC to over 250 kHz.
5.0 POWER SUPPLY CONSIDERATIONS
The ADC10662 and ADC10664 are designed to operate
from a +5V (nominal) power supply. There are two supply
pins, AVCC and DVCC. These pins allow separate external
bypass capacitors for the analog and digital portions of the
circuit. To guarantee accurate conversions, the two supply
pins should be connected to the same voltage source, and
each should be bypassed with a 0.1 µF ceramic capacitor in
parallel with a 10 µF tantalum capacitor. Depending on the
circuit board layout and other system considerations, more
bypassing may be necessary.
The ADC10662 and ADC10664 have separate analog and
digital ground pins for separate bypassing of the analog and
digital supplies. Their ground pins should be connected to
the same potential, and all grounds should be “clean” and
free of noise.
In systems with multiple power supplies, careful attention to
power supply sequencing may be necessary to avoid over-
driving inputs. The A/D converter’s power supply pins should
be at the proper voltage before digital or analog signals are
applied to any of the other pins.
6.0 LAYOUT AND GROUNDING
In order to ensure fast, accurate conversions from the
ADC10662 and ADC10664, it is necessary to use appropri-
ate circuit board layout techniques. The analog ground re-
turn path should be low-impedance and free of noise from
other parts of the system. Noise from digital circuitry can be
especially troublesome, so digital grounds should always be
separate from analog grounds. For best performance, sepa-
rate ground planes should be provided for the digital and
analog parts of the system.
All bypass capacitors should be located as close to the con-
verter as possible and should connect to the converter and
to ground with short traces. The analog input should be iso-
lated from noisy signal traces to avoid having spurious sig-
nals couple to the input. Any external component (e.g., a fil-
ter capacitor) connected across the converter’s input should
be connected to a very clean ground return point. Grounding
the component at the wrong point will result in reduced con-
version accuracy.
7.0 DYNAMIC PERFORMANCE
Many applications require the A/D converter to digitize AC
signals, but conventional DC integral and differential nonlin-
earity specifications don’t accurately predict the A/D convert-
er’s performance with AC input signals. The important speci-
fications for AC applications reflect the converter’s ability to
digitize AC signals without significant spectral errors and
without adding noise to the digitized signal. Dynamic charac-
teristics such as signal-to-noise ratio (SNR) and total har-
monic distortion (THD), are quantitative measures of this ca-
pability.
11 www.national.com
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ADC10662.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ADC10662 | 10-Bit 360 ns A/D Converter with Input Multiplexer and Sample/Hold | National Semiconductor |
| ADC10662CIWM | 10-Bit 360 ns A/D Converter with Input Multiplexer and Sample/Hold | National Semiconductor |
| ADC10664 | 10-Bit 360 ns A/D Converter with Input Multiplexer and Sample/Hold | National Semiconductor |
| ADC10664 | 10-Bit 360-ns ADC w/Input Multiplexer and Sample/Hold (Rev. E) |  Texas Instruments |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |