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PDF ADC10061 Data sheet ( Hoja de datos )
| Número de pieza | ADC10061 | |
| Descripción | 10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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June 1999
ADC10061/ADC10062/ADC10064
10-Bit 600 ns A/D Converter with Input Multiplexer and
Sample/Hold
General Description
Using an innovative, patented multistep* conversion tech-
nique, the 10-bit ADC10061, ADC10062, and ADC10064
CMOS analog-to-digital converters offer sub-microsecond
conversion times yet dissipate a maximum of only 235 mW.
The ADC10061, ADC10062, and ADC10064 perform a
10-bit conversion in two lower-resolution “flashes”, thus
yielding a fast A/D without the cost, power dissipation, and
other problems associated with true flash approaches. The
ADC10061 is pin-compatible with the ADC1061 but much
faster, thus providing a convenient upgrade path for the
ADC1061.
The analog input voltage to the ADC10061, ADC10062, and
ADC10064 is sampled and held by an internal sampling cir-
cuit. Input signals at frequencies from dc to over 200 kHz
can therefore be digitized accurately without the need for an
external sample-and-hold circuit.
The ADC10062 and ADC10064 include a “speed-up” pin.
Connecting an external resistor between this pin and ground
reduces the typical conversion time to as little as 350 ns with
only a small increase in linearity error.
For ease of interface to microprocessors, the ADC10061,
ADC10062, and ADC10064 have been designed to appear
as a memory location or I/O port without the need for exter-
nal interface logic.
*U.S. Patent Number 4918449
Features
n Built-in sample-and-hold
n Single +5V supply
n 1, 2, or 4-input multiplexer options
n No external clock required
n Speed adjust pin for faster conversions (ADC10062
and ADC10064). See ADC10662/4 for high speed
guaranteed performance.
Key Specifications
n Conversion time to 10 bits
600 ns typical,
n 900 ns max over temperature
n Sampling Rate
800 kHz
n Low power dissipation
235 mW (max)
n Total unadjusted error
±1.0 LSB (max)
n No missing codes over temperature
Applications
n Digital signal processor front ends
n Instrumentation
n Disk drives
n Mobile telecommunications
Simplified Block Diagram
*ADC10061 Only
**ADC10062 and ADC10064 Only
***ADC10064 Only
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS011020
DS011020-1
www.national.com
1 page  
DC Electrical Characteristics (Continued)
The
wise
following specifications apply for V+ =
specified. Boldface limits apply for
+5V,
TA =
TVJR=EFT(+M) I=N
5V VREF(−) = GND, and
to TMAX; all other limits
Speed Adjust pin
TA = TJ = +25˚C.
unconnected
unless
other-
Symbol
Parameter
Conditions
Typical
(Note 7)
Limit
(Note 8)
Units
(Limit)
VOUT(0)
IOUT
DICC
AICC
Logical “0” Output Voltage
TRI-STATE® Output Current
DVCC Supply Current
AVCC Supply Current
V+ = 4.5V, IOUT = 1.6 mA
VOUT = 5V
VOUT = 0V
CS = S/H = RD = 0, RSA = ∞
CS = S/H = RD = 0, RSA = 18 kΩ
CS = S/H = RD = 0, RSA = ∞
CS = S/H = RD = 0, RSA = 18 kΩ
0.4 V (max)
0.1 50 µA (max)
−0.1
−50 µA (max)
1.0 mA (max)
1.0 2 mA (max)
30 mA (max)
30 45 mA (max)
AC Electrical Characteristics
The following specifications apply for V+ = +5V, tr = tf = 20 ns, VREF(+) = 5V, VREF(−) = GND, and Speed Adjust pin uncon-
nected unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25˚C.
Symbol
Parameter
Conditions
Typical
(Note 7)
Limit
(Note 8)
Units
(Limit)
tCONV
Mode 1 Conversion Time from
Rising Edge of S/H to Falling Edge
of INT
RSA = ∞
RSA = 18k
600
750/900
ns(max)
375 ns
tCRD
tACC1
Mode 2 Conversion Time
Access Time (Delay from Falling
Edge of RD to Output Valid)
RSA = ∞
Mode 2, RSA = 18k
Mode 1; CL = 100 pF
850
1400
ns(max)
530 ns
30 60 ns (max)
tACC2
Access Time (Delay from Falling
Edge of RD to Output Valid)
Mode 2; CL = 100 pF
900
tCRD + 50
ns (max)
tSH
t1H, t0H
Minimum Sample Time
TRI-STATE Control (Delay from
Rising Edge of RD to High-Z State)
(Figure 1); (Note 8)
RL = 1k, CL = 10 pF
250 ns (max)
30 60 ns (max)
tINTH
Delay from Rising Edge of RD to
Rising Edge of INT
CL = 100 pF
25 50 ns (max)
tP Delay from End of Conversion to
Next Conversion
50 ns (max)
tMS
tMH
CVIN
COUT
CIN
Multiplexer Control Setup Time
Multiplexer Hold Time
Analog Input Capacitance
Logic Output Capacitance
Logic Input Capacitance
10 75 ns (max)
10 40 ns (max)
35 pF (max)
5 pF (max)
5 pF (max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed
test conditons.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND or VIN > V+) the absolute value of current at that pin should be limited
to 5 mA or less. The 20 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD = (TJMAX − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. In most cases,
the maximum derated power dissipation will be reached only during fault conditions. For these devices, TJMAX for a board-mounted device can be found from the
tables below:
Device
ADC10061CIWM
θJA (˚C/W)
54
ADC10062CIWM
48
ADC10064CIWM
44
Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 6: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in a current National Semicon-
ductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Typicals are at +25˚C and represent must likely parametric norm.
5 www.national.com
5 Page 
Applications Information (Continued)
DS011020-15
FIGURE 4. Typical Connection. Note the multiple bypass capacitors on the reference and power supply pins. If VREF−
is not grounded, it should also be bypassed to analog ground using multiple capacitors (see 5.0 “Power Supply
Considerations”). AGND and DGND should be at the same potential. VIN0 is shown with an input protection network.
Pin 17 is normally left open, but optional “speedup” resistor RSA can be used to reduce the conversion time.
4.0 INHERENT SAMPLE-AND-HOLD
Because the ADC10061, ADC10062, and ADC10064
sample the input signal once during each conversion, they
are capable of measuring relatively fast input signals without
the help of an external sample-hold. In a non-sampling
successive-approximation A/D converter, regardless of
speed, the input signal must be stable to better than ±1/2
LSB during each conversion cycle or significant errors will
result. Consequently, even for many relatively slow input sig-
nals, the signals must be externally sampled and held con-
stant during each conversion if a SAR with no internal
sample-and-hold is used.
Because they incorporate a direct sample/hold control input,
the ADC10061, ADC10062, and ADC10064 are suitable for
use in DSP-based systems. The S/H input allows synchroni-
zation of the A/D converter to the DSP system’s sampling
rate and to other ADC10061s, ADC10062s, and
ADC10064s.
The ADC10061, ADC10062, and ADC10064 can perform ac-
curate conversions of input signals with frequency compo-
nents from DC to over 160 kHz.
5.0 POWER SUPPLY CONSIDERATIONS
The ADC10061, ADC10062, and ADC10064 are designed to
operate from a +5V (nominal) power supply. There are two
supply pins, AVCC and DVCC. These pins allow separate ex-
ternal bypass capacitors for the analog and digital portions of
the circuit. To guarantee accurate conversions, the two sup-
ply pins should be connected to the same voltage source,
and each should be bypassed with a 0.1 µF ceramic capaci-
tor in parallel with a 10 µF tantalum capacitor. Depending on
the circuit board layout and other system considerations,
more bypassing may be necessary.
The ADC10061 has a single ground pin, and the ADC10062
and ADC10064 each have separate analog and digital
ground pins for separate bypassing of the analog and digital
supplies. The devices with separate analog and digital
ground pins should have their ground pins connected to the
same potential, and all grounds should be “clean” and free of
noise.
In systems with multiple power supplies, careful attention to
power supply sequencing may be necessary to avoid over-
driving inputs. The A/D converter’s power supply pins should
be at the proper voltage before digital or analog signals are
applied to any of the other pins.
6.0 LAYOUT AND GROUNDING
In order to ensure fast, accurate conversions from the
ADC10061, ADC10062, and ADC10064, it is necessary to
use appropriate circuit board layout techniques. The analog
ground return path should be low-impedance and free of
noise from other parts of the system. Noise from digital cir-
cuitry can be especially troublesome, so digital grounds
should always be separate from analog grounds. For best
performance, separate ground planes should be provided for
the digital and analog parts of the system.
All bypass capacitors should be located as close to the con-
verter as possible and should connect to the converter and
to ground with short traces. The analog input should be iso-
lated from noisy signal traces to avoid having spurious sig-
nals couple to the input. Any external component (e.g., a fil-
ter capacitor) connected across the converter’s input should
be connected to a very clean ground return point. Grounding
the component at the wrong point will result in reduced con-
version accuracy.
7.0 DYNAMIC PERFORMANCE
Many applications require the A/D converter to digitize AC
signals, but conventional DC integral and differential nonlin-
earity specifications don’t accurately predict the A/D convert-
er’s performance with AC input signals. The important speci-
fications for AC applications reflect the converter’s ability to
11 www.national.com
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ADC10061.PDF ] | |
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