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PDF ADC10040 Data sheet ( Hoja de datos )
| Número de pieza | ADC10040 | |
| Descripción | 10-Bit/ 40 MSPS/ 3V/ 55.5 mW A/D Converter | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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November 2004
ADC10040
10-Bit, 40 MSPS, 3V, 55.5 mW A/D Converter
General Description
The ADC10040 is a monolithic CMOS analog-to-digital con-
verter capable of converting analog input signals into 10-bit
digital words at 40 Megasamples per second (MSPS). This
converter uses a differential, pipeline architecture with digital
error correction and an on-chip sample-and-hold circuit to
provide a complete conversion solution, and to minimize
power consumption, while providing excellent dynamic per-
formance. A unique sample-and-hold stage yields a full-
power bandwidth of 400 MHz. Operating on a single 3.0V
power supply, this device consumes just 55.5 mW at
40 MSPS, including the reference current. The Standby
feature reduces power consumption to just 13.5 mW.
The differential inputs provide a full scale selectable input
swing of 2.0 VP-P, 1.5 VP-P, 1.0 VP-P, with the possibility of a
single-ended input. Full use of the differential input is recom-
mended for optimum performance. An internal +1.2V preci-
sion bandgap reference is used to set the ADC full-scale
range, and also allows the user to supply a buffered refer-
enced voltage for those applications requiring increased ac-
curacy. The output data format is 10-bit offset binary, or two’s
complement.
This device is available in the 28-lead TSSOP package and
will operate over the industrial temperature range of −40˚C to
+85˚C.
Features
n Single +3.0V operation
n Selectable 2.0 VP-P, 1.5 VP-P, or 1.0 VP-P full-scale input
swing
n 400 MHz −3 dB input bandwidth
n Low power consumption
n Standby mode
n On-chip reference and sample-and-hold amplifier
n Offset binary or two’s complement data format
n Separate adjustable output driver supply to
accommodate 2.5V and 3.3V logic families
n 28-pin TSSOP package
Key Specifications
n Resolution
n Conversion Rate
n Full Power Bandwidth
n DNL
n SNR (fIN = 11 MHz)
n SFDR (fIN = 11 MHz)
n Data Latency
n Supply Voltage
n Power Consumption, 40 MHz
10 Bits
40 MSPS
400 MHz
±0.3 LSB (typ)
59.6 dB (typ)
−80 dB (typ)
6 Clock Cycles
+3.0V
55.5 mW
Applications
n Ultrasound and Imaging
n Instrumentation
n Cellular Based Stations/Communications Receivers
n Sonar/Radar
n xDSL
n Wireless Local Loops
n Data Acquisition Systems
n DSP Front Ends
Connection Diagram
© 2004 National Semiconductor Corporation DS200778
20077801
www.national.com
1 page  
Absolute Maximum Ratings (Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VDDA, VDDIO
Voltage on Any Pin to GND
Input Current on Any Pin
Package Input Current (Note 3)
Package Dissipation at T = 25˚C
ESD Susceptibility
Human Body Model (Note 5)
Machine Model (Note 5)
Soldering Temperature
Infrared, 10 sec. (Note 6)
Storage Temperature
3.9V
−0.3V to VDDA or
VDDIO +0.3V
±25 mA
±50 mA
See (Note 4)
2500V
250V
235˚C
−65˚C to +150˚C
Operating Ratings
Operating Temperature Range
−40˚C ≤ TA ≤ +85˚C
VDDA (Supply Voltage)
+2.7V to +3.6V
VDDIO (Output Driver Supply
Voltage)
+2.5V to VDDA
VREF
1.20V
|VSSA– VSSIO|
≤ 100 mV
NOTE: Absolute maximum ratings are limiting values, to be applied individu-
ally, and beyond which the serviceability of the circuit may be impaired.
Functional operability under any of these conditions is not necessarily im-
plied. Exposure to maximum ratings for extended periods may affect device
reliability.
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V,
VIN = 2 VP-P, STBY = 0V, VREF = 1.20V, (External Supply) fCLK = 40 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface limits
apply for TA = TMIN to TMAX: all other limits TA = 25˚C.
Symbol
Parameter
Conditions
Min Typ Max Units
STATIC CONVERTER CHARACTERISTICS
No Missing Codes Guaranteed
10 Bits
INL
Integral Non-Linearity (Note 11)
FIN = 250 kHz, −0 dB Full
−1.0
Scale
±0.3
+1.0
LSB
DNL
Differential Non-Linearity
FIN = 250 kHz, −0 dB Full
Scale
−0.9
±0.3
+0.9
LSB
GE Gain Error
Positive Error
Negative Error
−1.5
−1.5
+0.4
−0.01
+1.9
+1.9
% FS
% FS
OE Offset Error (VIN+ = VIN−)
Under Range Output Code
−1.4
0.12
0
+1.6
% FS
Over Range Output Code
1023
FPBW Full Power Bandwidth
400 MHz
REFERENCE AND INPUT CHARACTERISTICS
VCM Common Mode Input Voltage
Output Voltage for use as an
0.5 1.5 V
1.45
VCOM
input common mode voltage
(Note 16)
V
VREF
VREFTC
Reference Voltage
Reference Voltage Temperature
Coefficient
1.2 V
±80 ppm/˚C
POWER SUPPLY CHARACTERISTICS
IVDDA
Analog Supply Current
STBY = 1
STBY = 0
4.5 6.0
18 25
mA
mA
IVDDIO
PWR
Digital Supply Current
Power Consumption
STBY = 1, fIN = 0 Hz
STBY = 0, fIN = 0 Hz
STBY = 1
STBY = 0
0
0.6
13.5
55.5
0.8
18
77
mA
mA
mW
mW
5 www.national.com
5 Page 
Typical Performance Characteristics Unless otherwise specified, the following specifications apply:
VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 40 MHz,
fIN = 19 MHz, 50% Duty Cycle. (Continued)
INL vs. Clock Duty Cycle
SNR vs. VDDIO
SNR vs. VDDA
20077818
SNR vs. fCLK
20077819
INL vs. Temperature
20077820
20077821
SNR vs. Clock Duty Cycle
20077822
11
20077823
www.national.com
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ADC10040.PDF ] | |
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