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PDF ADC08351CIMTC Data sheet ( Hoja de datos )
| Número de pieza | ADC08351CIMTC | |
| Descripción | 8-Bit/ 42 MSPS/ 40 mW A/D Converter | |
| Fabricantes | National Semiconductor | |
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March 2000
ADC08351
8-Bit, 42 MSPS, 40 mW A/D Converter
General Description
The ADC08351 is an easy to use low power, low cost, small
size, 42 MSPS analog-to-digital converter that digitizes sig-
nals to 8 bits. The ADC08351 uses an unique architecture
that achieves 7.2 Effective Bits with a 4.4 MHz input and
42 MHz clock frequency and 6.8 Effective Bits with a 21 MHz
input and 42 MHz clock frequency. Output formatting is
straight binary coding.
To minimize system cost and power consumption, the
ADC08351 requires minimal external components and in-
cludes input biasing to allow optional a.c. input signal cou-
pling. The user need only provide a +3V supply and a clock.
Many applications require no separate reference or driver
components.
The excellent dc and ac characteristics of this device, to-
gether with its low power consumption and +3V single supply
operation, make it ideally suited for many video and imaging
applications, including use in portable equipment. Total
power consumption is reduced to less than 7 mW in the
power-down mode. Furthermore, the ADC08351 is resistant
to latch-up and the outputs are short-circuit proof.
Fabricated on a 0.35 micron CMOS process, the ADC08351
is offered in TSSOP and is designed to operate over the
commercial temperature range of −20˚C to +85˚C.
Features
n Low Input Capacitance
n Internal Sample-and-Hold Function
n Single +3V Operation
n Power Down Feature
n TRI-STATE® Outputs
Key Specifications
n Resolution
8 Bits
n Maximum Sampling Frequency
42 MSPS (min)
n ENOB @ fCLK = 42 MHz, fIN = 4.4 MHz 7.2 Bits (typ)
n Guaranteed No Missing Codes
n Power Consumption
40 mW (typ); 48 mW (max)
(Excluding Reference Current)
Applications
n Video Digitization
n Digital Still Cameras
n Set Top Boxes
n Digital Camcorders
n Communications
n Medical Imaging
n Personal Computer Video
n CCD Imaging
n Electro-Optics
Pin Configuration
Ordering Information
ADC08351CIMTC
ADC08351CIMTCX
TSSOP
TSSOP (tape & reel)
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS100895
DS100895-1
www.national.com
1 page  
Converter Electrical Characteristics (Continued)
The following specifications apply for VA = VD = +3.0 VDC, VREF = 2.4V, VIN = 1.63 VP-P, OE = 0V, CL = 20 pF,
fCLK = 42 MHz, 50% duty cycle, unless otherwise specified.
Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C (Notes 7, 8)
Symbol
Parameter
Conditions
Typical Limits
(Note 9) (Note 9)
Units
(Limits)
Digital Output Characteristics
IOH High Level Output Current
IOL Low Level Output Current
VOH High Level Output Voltage
VOL Low Level Output Voltage
IOZH,
IOZL
TRI-STATE Output Current
AC Electrical Characteristics
VD = 2.7V, VOH = VD −0.5V
VD = 2.7V, OE = DGND, VOL = 0.4V
VD = 2.7V, IOH = −360 µA
VD = 2.7V, IOL = 1.6 mA
OE = VD = 3.3V, VOH = 3.3V or VOL = 0V
2.65
0.2
±10
−1.1
1.8
mA (min)
mA (min)
V
V
µA
fC1 Maximum Conversion Rate
fC2 Minimum Conversion Rate
tOD Output Delay
CLK High to Data Valid
Pipline Delay (Latency)
42 MHz (min)
2 MHz
14 19 ns (max)
2.5 Clock
Cycles
tDS
Sampling (Aperture) Delay
CLK Low to Acquisition of Data
2
ns
tOH Output Hold Time
CLK High to Data Invalid
9 ns
tEN OE Low to Data Valid
Loaded as in Figure 2
14 ns
tDIS OE High to High Z State
Loaded as in Figure 2
10 ns
fCLK = 30 MHz, fIN = 1 MHz 7.2 Bits
ENOB Effective Number of Bits
fCLK = 42 MHz, fIN = 4.4 MHz
7.2
Bits
fCLK = 42 MHz, fIN = 21 MHz
6.8 6.1 Bits (min)
fCLK = 30 MHz, fIN = 1 MHz 45 dB
SINAD Signal-to-Noise & Distortion
fCLK = 42 MHz, fIN = 4.4 MHz
45
dB
fCLK = 42 MHz, fIN = 21 MHz
43 38.5 dB (min)
fCLK = 30 MHz, fIN = 1 MHz 44 dB
SNR
Signal-to-Noise Ratio
fCLK = 42 MHz, fIN = 4.4 MHz
45
dB
fCLK = 42 MHz, fIN = 21 MHz
44 41 dB (min)
fCLK = 30 MHz, fIN = 1 MHz −57 dB
THD
Total Harmonic Distortion
fCLK = 42 MHz, fIN = 4.4 MHz
−51
dB
fCLK = 42 MHz, fIN = 21 MHz
−46 −41 dB (min)
fCLK = 30 MHz, fIN = 1 MHz 57 dB
SFDR
Spurious Free Dynamic Range fCLK = 42 MHz, fIN = 4.4 MHz
54
dB
fCLK = 42 MHz, fIN = 21 MHz
49 41 dB (min)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed speci-
fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than AGND or DGND, or greater than VA or VD), the current at that pin should
be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of
25 mA to two.
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax - TA)/θJA. For the 20-pin
TSSOP, θJA is 135˚C/W, so PDMAX = 926 mW at 25˚C and 481 mW at the maximum operating ambient temperature of 85˚C. Note that the power dissipation of this
device under normal operation will typically be about 68 mW (40 mW quiescent power + 23 mW reference ladder power + 5 mW due to 1 TTL loan on each digital
output). The values for maximum power dissipation listed above will be reached only when the ADC08351 is operated in a severe fault condition (e.g., when input
or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 6: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: All inputs are protected as shown below. Input voltage magnitudes up to 500 mV above the supply voltage or 500 mV below GND will not damage this device.
However, errors in the A/D conversion can occur if the input goes above VA or below AGND by more than 300 mV. As an example, if VA is 3.0 VDC, the full-scale
input voltage must be ≤3.3 VDC to ensure accurate conversions.
5 www.national.com
5 Page 
Applications Information (Continued)
ac performance, isolating the ADC clock from any digital cir-
cuitry should be done with adequate buffers, as with a clock
tree. See Figure 4.
It is good practice to keep the ADC clock line as short as
possible and to keep it well away from any other signals.
Other signals can introduce jitter into the clock signal. Even
lines with 90˚ crossings have capacitive coupling, so try to
avoid even these 90˚ crossings of the clock line.
DS100895-26
FIGURE 4. Isolating the ADC Clock from Digital
Circuitry
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have signifi-
cant impact upon system noise performance. The best logic
family to use in systems with A/D converters is one which
employs non-saturating transistor designs, or has low noise
characteristics, such as the 74HC(T) and 74AC(T)Q families.
The worst noise generators are logic families that draw the
largest supply current transients during clock or signal
edges, like the 74F and the 74AC(T) families. In general,
slower logic families, such as 74LS and 74HC(T) will pro-
duce less high frequency noise than do high speed logic
families, such as the 74F and 74AC(T) families.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
An effective way to control ground noise is by connecting the
analog and digital ground planes together beneath the ADC
with a copper trace that is narrow compared with the rest of
the ground plane. This narrowing beneath the converter pro-
vides a fairly high impedance to the high frequency compo-
nents of the digital switching currents, directing them away
from the analog pins. The relatively lower frequency analog
ground currents do not create a significant variation across
the impedance of this relatively narrow ground connection.
5.0 TYPICAL APPLICATION CIRCUITS
Figure 5 shows a simple interface for a low impedance
source located close to the converter. As discussed in Sec-
tion 1.0, the series capacitor is optional. Notice the isolation
of the ADC clock signal from the clock signals going else-
where in the system. The reference input of this circuit is
shown connected to the 3V supply.
Video ADCs tend to have input current transients that can
upset a driving source, causing distortion of the driving sig-
nal. The resistor at the ADC08351 input isolates the amplifi-
er’s output from the current transients at the input to the con-
verter.
When the signal source is not located close to the converter,
the signal should be buffered. Figure 6 shows an example of
an appropriate buffer. The amplifier provides a gain of two to
compensate for transmission losses.
Operational amplifiers have better linearity when they oper-
ate with gain, so the input is attenuated with the 68Ω and
30Ω resistors at the non-inverting input. The 330Ω resistor in
parallel with these two resistors provides for a 75Ω cable ter-
mination. Replacing this 330Ω resistor with one of 100Ω will
provide a 50Ω termination.
The circuit shown has a nominal gain of two. You can provide
a gain adjustment by changing the 110Ω feedback resistor to
a 100Ω resistor in series with a 20Ω potentiometer.
The offset adjustment is used to bring the input signal within
the common mode range of the converter. If a fixed offset is
desired, the potentiometer and the 3.3k resistor may be re-
placed with a single resistor of 3k to 4k to the appropriate
supply. The resistor value and the supply polarity used will
depend upon the amount and polarity of offset needed.
The CLC409 shown in Figure 6 was chosen for a low cost
solution with good overall performance.
Figure 7 shows an inverting DC coupled circuit. The above
comments regarding Figure 6 generally apply to this circuit
as well.
11 www.national.com
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| PDF Descargar | [ Datasheet ADC08351CIMTC.PDF ] | |
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