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PDF ADC0817CCN Data sheet ( Hoja de datos )
| Número de pieza | ADC0817CCN | |
| Descripción | 8-Bit P Compatible A/D Converters with 16-Channel Multiplexer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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June 1999
ADC0816/ADC0817
8-Bit µP Compatible A/D Converters
with 16-Channel Multiplexer
General Description
The ADC0816, ADC0817 data acquisition component is a
monolithic CMOS device with an 8-bit analog-to-digital con-
verter, 16-channel multiplexer and microprocessor compat-
ible control logic. The 8-bit A/D converter uses successive
approximation as the conversion technique. The converter
features a high impedance chopper stabilized comparator, a
256R voltage divider with analog switch tree and a succes-
sive approximation register. The 16-channel multiplexer can
directly access any one of 16-single-ended analog signals,
and provides the logic for additional channel expansion. Sig-
nal conditioning of any analog input signal is eased by direct
access to the multiplexer output, and to the input of the 8-bit
A/D converter.
The device eliminates the need for external zero and
full-scale adjustments. Easy interfacing to microprocessors
is provided by the latched and decoded multiplexer address
inputs and latched TTL TRI-STATE® outputs.
The design of the ADC0816, ADC0817 has been optimized
by incorporating the most desirable aspects of several A/D
conversion techniques. The ADC0816, ADC0817 offers high
speed, high accuracy, minimal temperature dependence, ex-
cellent long-term accuracy and repeatability, and consumes
minimal power. These features make this device ideally
suited to applications from process and machine control to
consumer and automotive applications. For similar perfor-
mance in an 8-channel, 28-pin, 8-bit A/D converter, see the
ADC0808, ADC0809 data sheet. (See AN-258 for more in-
formation.)
Features
n Easy interface to all microprocessors
n Operates ratiometrically or with 5 VDC or analog span
adjusted voltage reference
n 16-channel multiplexer with latched control logic
n Outputs meet TTL voltage level specifications
n 0V to 5V analog input voltage range with single 5V
supply
n No zero or full-scale adjust required
n Standard hermetic or molded 40-pin DIP package
n Temperature range −40˚C to +85˚C or −55˚C to +125˚C
n Latched TRI-STATE output
n Direct access to “comparator in” and “multiplexer out” for
signal conditioning
n ADC0816 equivalent to MM74C948
n ADC0817 equivalent to MM74C948-1
Key Specifications
n Resolution
n Total Unadjusted Error
n Single Supply
n Low Power
n Conversion Time
8 Bits
±1⁄2 LSB and ±1 LSB
5 VDC
15 mW
100 µs
Block Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS005277
DS005277-1
www.national.com
1 page  
Functional Description
Multiplexer: The device contains a 16-channel single-ended
analog signal multiplexer. A particular input channel is se-
lected by using the address decoder. Table 1 shows the input
states for the address line and the expansion control line to
select any channel. The address is latched into the decoder
on the low-to-high transition of the address latch enable sig-
nal.
Selected
Analog Channel
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
IN11
IN12
IN13
IN14
IN15
All Channels OFF
X=don’t care
TABLE 1.
Address Line
DCBA
LLLL
L L LH
L LHL
L LHH
LHL L
LHLH
L HH L
L HHH
HL L L
HL LH
HLHL
H L HH
HHL L
HH L H
HHH L
HHHH
XXXX
Expansion
Control
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
Additional single-ended analog signals can be multiplexed to
the A/D converter by disabling all the multiplexer inputs using
the expansion control. The additional external signals are
connected to the comparator input and the device ground.
Additional signal conditioning (i.e., prescaling, sample and
hold, instrumentation amplification, etc.) may also be added
between the analog input signal and the comparator input.
CONVERTER CHARACTERISTICS
The Converter
The heart of this single chip data acquisition system is its
8-bit analog-to-digital converter. The converter is designed to
give fast, accurate, and repeatable conversions over a wide
range of temperatures. The converter is partitioned into 3
major sections: the 256R ladder network, the successive ap-
proximation register, and the comparator. The converter’s
digital outputs are positive true.
The 256R ladder network approach Figure 1 was chosen
over the conventional R/2R ladder because of its inherent
monotonicity, which guarantees no missing digital codes.
Monotonicity is particularly important in closed loop feedback
control systems. A non-monotonic relationship can cause os-
cillations that will be catastrophic for the system. Additionally,
the 256R network does not cause load variations on the ref-
erence voltage.
The bottom resistor and the top resistor of the ladder net-
work in Figure 1 are not the same value as the remainder of
the network. The difference in these resistors causes the
output characteristic to be symmetrical with the zero and
full-scale points of the transfer curve. The first output transi-
tion occurs when the analog signal has reached + 1⁄2 LSB
and succeeding output transitions occur every 1 LSB later up
to full-scale.
DS005277-2
FIGURE 1. Resistor Ladder and Switch Tree
5
www.national.com
5 Page 
Applications Information (Continued)
DS005277-15
FIGURE 13. Symmetrically Centered Reference
3.0 CONVERTER EQUATIONS
The transition between adjacent codes N and N + 1 is given
by:
The center of an output code N is given by:
(2)
(3)
The output code N for an arbitrary input are the integers
within the range:
VREF(+) ÷512)
4.0 ANALOG COMPARATOR INPUTS
The dynamic comparator input current is caused by the pe-
riodic switching of on-chip stray capacitances These are
connected alternately to the output of the resistor ladder/
switch tree network and to the comparator input as part of
the operation of the chopper stabilized comparator.
The average value of the comparator input current varies di-
rectly with clock frequency and with VIN as shown in Figure
6.
If no filter capacitors are used at the analog or comparator in-
puts and the signal source impedances are low, the com-
parator input current should not introduce converter errors,
as the transient created by the capacitance discharge will die
out before the comparator output is strobed.
where: VIN = Voltage at comparator input
VREF = Voltage at Ref(+)
(4) If input filter capacitors are desired for noise reduction and
signal conditioning they will tend to average out the dynamic
comparator input current. It will then take on the characteris-
tics of a DC bias current whose effect can be predicted con-
VREF = Voltage at Ref(−)
ventionally. See AN-258 for further discussion.
VTUE = Total unadjusted error voltage (typically
11 www.national.com
11 Page | ||
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