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PDF ADC08161CIWM Data sheet ( Hoja de datos )
| Número de pieza | ADC08161CIWM | |
| Descripción | 500 ns A/D Converter with S/H Function and 2.5V Bandgap Reference | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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June 1999
ADC08161
500 ns A/D Converter with S/H Function and
2.5V Bandgap Reference
General Description
Using a patented multi-step A/D conversion technique, the
8-bit ADC08161 CMOS A/D converter offers 500 ns conver-
sion time, internal sample-and-hold (S/H), a 2.5V bandgap
reference, and dissipates only 100 mW of power. The
ADC08161 performs an 8-bit conversion with a 2-bit voltage
estimator that generates the 2 MSBs and two low-resolution
(3-bit) flashes that generate the 6 LBSs.
Input signals are tracked and held by the input sampling cir-
cuitry, eliminating the need for an external sample-and-hold.
The ADC08161 can perform accurate conversions of
full-scale input signals at frequencies from DC to typically
more than 300 kHz (full power bandwidth) without the need
of an external sample-and-hold (S/H).
For ease of interface to microprocessors, this part has been
designed to appear as a memory location or I/O port without
the need for external interfacing logic.
Key Specifications
n Resolution
n Conversion time (tCONV)
n Full power bandwidth
n Throughput rate
n Power dissipation
n Total unadjusted error
8 Bits
560 ns max (WR-RD Mode)
300 kHz (typ)
1.5 MHz min
100 mW max
±1⁄2 LSB and ±1 LSB max
Features
n No external clock required
n Analog input voltage range from GND to V+
n 2.5V bandgap reference
Applications
n Mobile telecommunications
n Hard-disk drives
n Instrumentation
n High-speed data acquisition systems
Block Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS011149
DS011149-1
www.national.com
1 page  
DC Electrical Characteristics (Continued)
The following specifications apply
all other limits TA = TJ = 25˚C.
for
V+
=
5V
unless
otherwise
specified.
Boldface
limits
apply
for
TA
=
TJ
=
TMIN
to
TMAX;
Symbol
Parameter
Conditions
Typical
(Note 7)
Limit
(Note 8)
Units
(Limit)
VIL Logic “0” Input Voltage
V+ = 4.5V
CS, WR, RD, A0, A1, A2 Pins
0.8 V (max)
Mode Pin
1.5
IIH Logic “1” Input Current
VH = 5V
CS, RD, A0, A, A2 Pins
0.005
1
WR Pin
0.1 3 µA (max)
Mode Pin
50 200
IIL Logic “0” Input Current
VL = 0V
CS, RD, WR, A0, A1, A2
Mode Pins
−0.005
−2 µA (max)
VOH Logic “1” Output Voltage
V+ = 4.75V
IOUT = −360 µA
DB0–DB7, OFL, INT
2.4 V (min)
IOUT = −10 µA
DB0–DB7, OFL, INT
4.5 V (min)
VOL Logic “0” Output Voltage
V+ = 4.75V
IOUT = 1.6 mA
DB0–DB7, OFL, INT, RDY
0.4 V (max)
IO TRI-STATE Output Current VOUT = 5.0V
DB0–DB7, RDY
0.1 3 µA (max)
VOUT = 0V
DB0–DB7, RDY
−0.1
−3 µA (max)
ISOURCE Output Source Current
VOUT = 0V
DB0–DB7, OFL, INT
−26 −6 mA (min)
ISINK Output Sink Current
VOUT = 5V
DB0–DB7, OFL, INT, RDY
24
7 mA (min)
IC
COUT
CIN
Supply Current
Logic Output Capacitance
Logic Input Capacitance
CS = WR = RD = 0
11.5
5
5
20 mA (max)
pF
pF
Bandgap Reference Electrical Characteristics
The following specifications
limits TA = TJ = 25˚C.
apply
for
V+
=
5V
unless
otherwise
specified.
Boldface
limits
apply
for
TMIN
to
TMAX;
all
other
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 7)
(Note 8)
(Limit)
VREFOUT
∆VREF/∆T
Internal Reference Output Voltage
Internal Reference Temperature
Coefficient
2.5 ± 2.0%
V (max)
40 ppm/˚C
∆VREF/∆IL
Internal Reference Load
Regulation
Sourcing (0 ≤ IL ≤ +10 mA)
0.01
0.1 %/mA (max)
Line Regulation
4.75V ≤ V+ ≤ 5.25V
0.5 6.0 mV (max)
ISC
∆VREF/∆t
Short Circuit Current
Long Term Stability
Start-Up Time
VREV = 0V
V+: 0V→5V, CL = 220 µF
35
200
40
mA (max)
ppm/kHr
ms
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee performance limits.
For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some per-
formance characteristics may degrade when the device is not operated under the listed test conditions.
5 www.national.com
5 Page 
Application Information
DS011149-17
FIGURE 6. Block Diagram of the ADC08161 Multi-Step Flash Architecture
1.0 FUNCTIONAL DESCRIPTION
The ADC08161 performs an 8-bit analog-to-digital conver-
sion using a multi-step flash technique. The first flash gener-
ates the five most significant bits (MSBs) and the second
flash generates the three least significant bits (LSBs). Figure
6 shows the major functional blocks of the ADC08161
multi-step flash converter. It consists of an over-encoded
21⁄2-bit Voltage Estimator, an internal DAC with two different
voltage spans, a 3-bit half-flash converter and a comparator
multiplexer.
The resistor string near the center of the block diagram in
Figure 6 forms the internal main DAC. Each of the eight re-
sistors at the bottom of the string is equal to 1/256 of the total
string resistance. These resistors form the LSB Ladder and
have a voltage drop of 1/256 of the total reference voltage
(VREF+ − VREF−) across them. The remaining resistors make
up the MSB Ladder . They are made up of eight groups of
four resistors connected in series. Each MSB Ladder section
has 1⁄8 of the total reference voltage across it. Within a given
MSB Ladder section, each of the MSB resistors has 8/256,
or 1⁄32 of the total reference voltage across it. Tap points are
found between all of the resistors in both the MSB and LSB
Ladders. Through the Comparator Multiplexer these tap
points can be connected, in groups of eight, to the eight com-
parators shown at the right of Figure 6. This function pro-
vides the necessary reference voltages to the comparators
during each flash conversion.
The six comparators, seven-resistor string (estimator DAC),
and Estimator Decoder at the left of Figure 6 form the Volt-
age Estimator. The estimator DAC connected between
VREF+ and VREF− generates the reference voltages for the
six Voltage Estimator comparators. These comparators per-
form a very low resolution A/D conversion to obtain an “esti-
mate” of the input voltage. This estimate is then used to con-
trol the Comparator Multiplexer, connecting the appropriate
MSB Ladder section to the eight flash comparators. Only 14
comparators, six in the Voltage Estimator and eight in the
flash converter, are needed to achieve the full eight-bit reso-
lution, instead of 32 comparators that would be needed by
traditional half-flash methods.
A conversion begins with the Voltage Estimator comparing
the analog input signal against the six tap voltages on the es-
timator DAC. The estimator decoder then selects one of the
groups of tap points along the MSB Ladder. These eight tap
points are then connected to the eight flash comparators.
For example, if the analog input signal applied to VIN is be-
11 www.national.com
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| PDF Descargar | [ Datasheet ADC08161CIWM.PDF ] | |
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