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PDF AD9995 Data sheet ( Hoja de datos )
| Número de pieza | AD9995 | |
| Descripción | 12-Bit CCD Signal Processor with Precision Timing Generator | |
| Fabricantes | Analog Devices | |
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12-Bit CCD Signal Processor with
Precision Timing ™ Generator
AD9995
FEATURES
6-Phase Vertical Transfer Clock Support
Correlated Double Sampler (CDS)
6 dB to 42 dB 10-Bit Variable Gain Amplifier (VGA)
12-Bit 36 MHz A/D Converter
Black Level Clamp with Variable Level Control
Complete On-Chip Timing Generator
Precision Timing Core with <600 ps Resolution
On-Chip 3 V Horizontal and RG Drivers
2-Phase and 4-Phase H-Clock Modes
Electronic and Mechanical Shutter Modes
On-Chip Driver for External Crystal
On-Chip Sync Generator with External Sync Input
56-Lead LFCSP Package
APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
Industrial Imaging
GENERAL DESCRIPTION
The AD9995 is a highly integrated CCD signal processor for
digital still camera and camcorder applications. It includes a
complete analog front end with A/D conversion, combined with a
full-function programmable timing generator. The timing genera-
tor is capable of supporting both 4- and 6-phase vertical clocking.
A Precision Timing core allows adjustment of high speed clocks
with less than 600 ps resolution at 36 MHz operation.
The AD9995 is specified at pixel rates of up to 36 MHz. The
analog front end includes black level clamping, CDS, VGA,
and a 12-bit A/D converter. The timing generator provides all
the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate
pulses, substrate clock, and substrate bias control. Operation is
programmed using a 3-wire serial interface.
Packaged in a space-saving 56-lead LFCSP, the AD9995 is speci-
fied over an operating temperature range of –20°C to +85°C.
CCDIN
FUNCTIONAL BLOCK DIAGRAM
VRT VRB
CDS
6dB TO 42dB
VGA
VREF
AD9995
12-BIT
ADC
12
DOUT
RG
H1–H4
V1–V6
VSG1–VSG5
HORIZONTAL
4 DRIVERS
6
V-H
5 CONTROL
INTERNAL CLOCKS
CLAMP
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
INTERNAL
REGISTERS
DCLK
MSHUT
STROBE
VSUB SUBCK
HD VD SYNC CLI CLO SL SCK DATA
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or oth-
erwise under any patent or patent rights of Analog Devices.Trademarks
and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
1 page  
AD9995
TIMING SPECIFICATIONS (CL = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, fCLI = 36 MHz, unless otherwise noted.)
Parameter
Symbol
Min Typ Max
MASTER CLOCK, CLI (Figure 4)
CLI Clock Period
CLI High/Low Pulsewidth
Delay from CLI Rising Edge to Internal Pixel Position 0
AFE CLPOB Pulsewidth1, 2 (Figures 9 and 14)
tCONV
tCLIDLY
27.8
11.2 13.9 16.6
6
2 20
AFE SAMPLE LOCATION1 (Figure 7)
SHP Sample Edge to SHD Sample Edge
DATA OUTPUTS (Figures 8a and 8b)
Output Delay from DCLK Rising Edge1
Pipeline Delay from SHP/SHD Sampling to DOUT
tS1
tOD
12.5 13.9
8
11
SERIAL INTERFACE (Figures 40a and 40b)
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
fSCLK
tLS
tLH
tDS
tDH
tDV
10
10
10
10
10
10
NOTES
1Parameter is programmable.
2Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
Specifications subject to change without notice.
Unit
ns
ns
ns
Pixels
ns
ns
Cycles
MHz
ns
ns
ns
ns
ns
ABSOLUTE MAXIMUM RATINGS*
Parameter
With
Respect
To Min
Max
Unit
AVDD
AVSS –0.3 +3.9
V
TCVDD
TCVSS –0.3 +3.9
V
HVDD
HVSS –0.3 +3.9
V
RGVDD
RGVSS –0.3 +3.9
V
DVDD
DVSS –0.3 +3.9
V
DRVDD
DRVSS –0.3 +3.9
V
RG Output
RGVSS –0.3 RGVDD + 0.3 V
H1–H4 Output
HVSS –0.3 HVDD + 0.3 V
Digital Outputs
DVSS
–0.3 DVDD + 0.3 V
Digital Inputs
DVSS
–0.3 DVDD + 0.3 V
SCK, SL, SDATA
DVSS
–0.3 DVDD + 0.3 V
REFT, REFB, CCDIN AVSS
–0.3 AVDD + 0.3 V
Junction Temperature
150 °C
Lead Temperature, 10 sec
350 °C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only. Functional operation of the device
at these or any other conditions above those listed in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability. Absolute maximum ratings apply
individually only, not in combination. Unless otherwise specified, all other voltages
are referenced to GND.
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance
JA = 25°C/W*
*JA is measured using a 4-layer PCB with the exposed paddle soldered to the
board.
Model
AD9995KCP
AD9995KCPRL
ORDERING GUIDE
Temperature
Range
Package
Description
–20°C to +85°C LFCSP
–20°C to +85°C LFCSP
Package
Option
CP-56
CP-56
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on
the human body and test equipment and can discharge without detection. Although the AD9995 features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
REV. 0
–5–
5 Page 
AD9995
mapped into four quadrants, with each quadrant containing 12
edge locations. Table II shows the correct register values for the
corresponding edge locations.
Figure 7 shows the default timing locations for all of the high
speed clock signals.
H-Driver and RG Outputs
In addition to the programmable timing positions, the AD9995
features on-chip output drivers for the RG and H1–H4 outputs.
These drivers are powerful enough to directly drive the CCD
inputs. The H-driver and RG current can be adjusted for optimum
rise/fall time into a particular load by using the DRVCONTROL
register (Addr. 0x35). The 3-bit drive setting for each output is
adjustable in 4.1 mA increments, with the minimum setting of 0
equal to OFF or three-state, and the maximum setting of 7 equal
to 30.1 mA.
As shown in Figures 5, 6, and 7, the H2 and H4 outputs are
inverses of H1 and H3, respectively. The H1/H2 crossover volt-
age is approximately 50% of the output swing. The crossover
voltage is not programmable.
Digital Data Outputs
The AD9995 data output and DCLK phases are programmable
using the DOUTPHASE register (Addr. 0x37, Bits [5:0]). Any
edge from 0 to 47 may be programmed, as shown in Figure 8a.
Normally, the DOUT and DCLK signals will track in phase
based on the DOUTPHASE register contents. The DCLK
output phase can also be held fixed with respect to the data out-
puts by changing the DCLKMODE register high (Addr. 0x37,
Bit 6). In this mode, the DCLK output will remain at a fixed
phase equal to CLO (the inverse of CLI) while the data output
phase is still programmable.
There is a fixed output delay from the DCLK rising edge to the
DOUT transition, called tOD. This delay can be programmed to
four values between 0 ns and 12 ns by using the DOUTDELAY
register (Addr. 0x037, Bits [8:7]). The default value is 8 ns.
The pipeline delay through the AD9995 is shown in Figure 8b.
After the CCD input is sampled by SHD, there is an 11-cycle
delay until the data is available.
Parameter
Polarity
Positive Edge
Negative Edge
Sampling Location
Drive Strength
Table I. Timing Core Register Parameters for H1, H3, RG, SHP/SHD
Length
Range
Description
1b High/Low
Polarity Control for H1, H3, and RG (0 = No Inversion, 1 = Inversion)
6b 0–47 Edge Location Positive Edge Location for H1, H3, and RG
6b 0–47 Edge Location Negative Edge Location for H1, H3, and RG
6b 0–47 Edge Location Sampling Location for Internal SHP and SHD Signals
3b 0–47 Current Steps Drive Current for H1–H4 and RG Outputs (4.1 mA per Step)
Quadrant
I
II
III
IV
CCD
SIGNAL
RG
H1/H3
H2/H4
USING THE SAME TOGGLE POSITIONS FOR H1 AND H3 GENERATES STANDARD 2-PHASE H-CLOCKING.
Figure 6. 2-Phase H-Clock Operation
Table II. Precision Timing Edge Locations
Edge Location (Dec)
Register Value (Dec)
0 to 11
12 to 23
24 to 35
36 to 47
0 to 11
16 to 27
32 to 43
48 to 59
Register Value (Bin)
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
REV. 0
–11–
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| PDF Descargar | [ Datasheet AD9995.PDF ] | |
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