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PDF AD9956 Data sheet ( Hoja de datos )
| Número de pieza | AD9956 | |
| Descripción | 2.7 GHz DDS-Based AgileRF | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD9956 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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2.7 GHz DDS-Based AgileRFTM Synthesizer
AD9956
FEATURES
400 MSPS internal DDS clock speed
48-bit frequency tuning word
14-bit programmable phase offset
Integrated 14-bit DAC
Excellent dynamic performance
Phase noise ≤ 135 dBc/Hz @ 1 KHz offset
−80 dB SFDR @ 160 MHz (±100 KHz offset IOUT)
25 Mb/s write-speed serial I/O control
200 MHz phase frequency detector inputs
655 MHz programmable input dividers for the phase
frequency detector (÷M, ÷N) {M, N = 1..16} (bypassable)
Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)
8 phase/frequency profiles
1.8 V supply for device operation
3.3 V supply for I/O and charge pump
Software controlled power-down
48-lead LFCSP package
Automatic linear frequency sweeping capability (in DDS)
Programmable charge pump current (up to 4 mA)
Phase modulation capability
Multichip synchronization
Dual-mode PLL lock detect
655 MHz CML-mode PECL-compliant driver
APPLICATIONS
Agile LO frequency synthesis
FM chirp source for radar and scanning systems
Automotive radars
Test and measurement equipment
Acousto-optic device drivers
FUNCTIONAL BLOCK DIAGRAM
DAC_RSET
DELTA
FREQUENCY
TUNING WORD
FREQUENCY
ACCUMULATOR
PLL_LOCK/SYNC_IN
I/O_UPDATE
DELTA
FREQUENCY
24 RAMP RATE
16
48 PHASE
OFFSET
19
FTW
48
PHASE
ACCUMULATOR
PHASE
OFFSET
WORD
14
DDS CORE
PHASE TO
AMPLITUDE
CONVERSION
SYSCLK
TIMING AND CONTROL LOGIC
14
DAC
SYSCLK
IOUT
IOUT
I/O_RESET
SYNC_OUT
REFCLK
REFCLK
SYNC_CLK
RF-DIVIDER
÷R
CML CLOCK DRIVER
SYSCLK
÷4
3
OSCILLATOR
BUFFER
LOCK
DETECT
÷M
Φ
÷N
CHARGE
PUMP
SCALER
3
CHARGE
PUMP
CP_OUT
FROM PLLOSC
BUFFER
DRV DRV DRV_RSET
PS<2:0> RESET I/O PORT PLLREF/ PLLOSC/
PLLREF PLLOSC
Figure 1.
CP_RSET
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
Parameter
LOGIC INPUTS (SDI/O, I/O_RESET, RESET,
I/O_UPDATE, PS0 to PS2, SYNC_IN)
VIH, Input High Voltage
VIL, Input Low Voltage
IINH, IINL Input Current
CIN, Maximum Input Capacitance
LOGIC OUTPUTS (SDO, SYNC_OUT, PLL_LOCK)6
VOH, Output High Voltage
VOH, Output Low Voltage
IOH
IOL
POWER CONSUMPTION
Total Power Consumed, All Functions On
IAVDD
IDVDD
IDVDD_I/O
ICP_VDD
Power-Down Mode
WAKE-UP TIME (from Power-Down Mode)
Digital Power-Down (CFR1<7>)
DAC Power-Down (CFR2<39>)
RF Divider Power-Down (CFR2<23>)
Clock Driver Power-Down (CFR2<20>)
Charge Pump Full Power-Down (CFR2<4>)
Charge Pump Quick Power-Down (CFR2<3>)
DAC OUTPUT CHARACTERISTICS
Resolution
Full-Scale Output Current
Gain Error
Output Offset
Output Capacitance
Voltage Compliance Range
Wideband SFDR (DC to Nyquist)
10 MHz Analog Out
40 MHz Analog Out
80 MHz Analog Out
120 MHz Analog Out
160 MHz Analog Out
Narrowband SFDR
10 MHz Analog Out (±1 MHz)
10 MHz Analog Out (±250 kHz)
10 MHz Analog Out (±50 kHz)
40 MHz Analog Out (±1 MHz)
40 MHz Analog Out (±250 kHz)
40 MHz Analog Out (±50 kHz)
80 MHz Analog Out (±1 MHz)
80 MHz Analog Out (±250 kHz)
80 MHz Analog Out (±50 kHz)
120 MHz Analog Out (±1 MHz)
120 MHz Analog Out (±250 kHz)
120 MHz Analog Out (±50 kHz)
Min Typ
2.0
±1
3
2.7
100
100
80
12
7
400
6
10
150
14
10
−10
5
AVDD − 0.50
−64
−62
−60
−55
−55
−89
−91
−93
−87
−89
−91
−85
−87
−89
−83
−85
−87
Max Unit
V
0.8 V
±5 µA
pF
V
0.4 V
µA
µA
400 mW
85 mA
45 mA
20 mA
15 mA
mW
ns
µs
ns
µs
µs
ns
15
+10
0.6
AVDD + 0.50
Bits
mA
% FS
µA
pF
V
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Rev. 0 | Page 5 of 32
AD9956
Test Conditions/Comments
5 Page 
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9956
AGND 1
AVDD 2
AGND 3
AVDD 4
IOUT 5
IOUT 6
AVDD 7
AGND 8
I/O_RESET 9
RESET 10
DVDD 11
DGND 12
NC = NO CONNECT
PIN 1
INDICATOR
AD9956
TOP VIEW
(Not to Scale)
36 CP_OUT
35 CP_VDD
34 AGND
33 DRV
32 DRV
31 AVDD
30 AGND
29 REFCLK
28 REFCLK
27 AVDD
26 AGND
25 DVDD
Figure 3. 48-Lead LFCSP Pin Configuration
Note that the exposed paddle on this package is an electrical connection (Pin 49) as well as a thermal enhancement. For the device to
function properly, the paddle MUST be attached to analog ground.
Rev. 0 | Page 11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9956.PDF ] | |
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