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PDF AD9870 Data sheet ( Hoja de datos )
| Número de pieza | AD9870 | |
| Descripción | IF Digitizing Subsystem | |
| Fabricantes | Analog Devices | |
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FEATURES
10 MHz–300 MHz Input Frequency
Baseband (I/Q) Digital Output
10 kHz–150 kHz Output Signal Bandwidth
12 dB SSB NF
> –1 dBm IIP3 (High IIP3 Mode)
25 dB Continuous AGC Range + 16 dB Gain Step
Support for LO and Sampling Clock Synthesis
Programmable Decimation Rate, Output Format, AAF
Cutoff, AGC and Synthesizer Settings
360 ⍀ Input Impedance
2.7 V–3.6 V Supply Voltage
Low Current: 42 mA Typ (High IIP3 Mode),
30 mA Typ (Low IIP3, Fixed Gain Mode)
48-Lead LQFP Package (1.4 mm Thick)
APPLICATIONS
Portable and Mobile Radio Products
Digital UHF/VHF FDMA Products
TETRA
IF Digitizing Subsystem
AD9870
PRODUCT DESCRIPTION
The AD9870 is a general-purpose IF subsystem that digitizes a
low-level 10 MHz–300 MHz IF input with a bandwidth of up to
150 kHz. The signal chain of the AD9870 consists of a low-noise
amplifier, a mixer, a variable gain amplifier with integral antialias
filter, a bandpass sigma-delta analog-to-digital converter, and a
decimation filter with programmable decimation factor. An auto-
matic gain control (AGC) circuit provides the AD9870 with
25 dB of continuous gain adjustment. The high dynamic range
of the bandpass sigma-delta converter allows the AD9870 to
cope with blocking signals that are as much as 70 dB stronger
than the desired signal. Auxiliary blocks include clock and LO
synthesizers as well as a serial peripheral interface (SPI) port.
The SPI port programs numerous parameters of the AD9870,
including the synthesizer divide ratios, the AGC attack and decay
times, the AGC target signal level, the decimation factor, the
output data format, the 16 dB attenuator, and the bias currents of
several blocks. Reducing bias currents allows the user to reduce
power consumption at the expense of reduced performance.
FUNCTIONAL BLOCK DIAGRAM
AD9870
–16dB
IFIN LNA
FREF
LO
SYNTH
DAC AGC
VGA /
AAF
⌺-⌬ ADC
fCLK = 18MHz
DECIMATION
FILTER
FORMATTING/SSI
SAMP CLOCK
SYNTHESIZER
VOLTAGE
REFERENCE
CONTROL LOGIC
SPI
DOUTA
DOUTB
FS
CLKOUT
LO VCO AND
LOOP FILTER
CLK VCO AND
LOOP FILTER
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
1 page  
AD9870
SERIAL PERIPHERAL INTERFACE (SPI)
The Serial Peripheral Interface (SPI) is a bidirectional serial port. It is used to load configuration information into the registers listed
below as well as to read back their contents. Table I provides a list of the registers that may be programmed through the SPI port.
Addresses and default values are given in hexadecimal form.
Table I. SPI Address Map
Address Bit
(Hex) Breakdown
Width Default Value Name
Description
POWER CONTROL REGISTERS
0x00 (7:0)
8 0xFF
STBY
Standby Control Bits (REF, LO, CKO, CK, GC, LNAMX, VGA, ADC).
0x01
(7:6)
(5:4)
(3:2)
(1:0)
20
20
20
21
LNAB
MIXB
CKOB
ADCB
LNA Bias Current (0 = 0.5 mA, 1 = 1 mA, 2 = 2 mA, 3 = 3 mA).
Mixer Bias Current (0 = 1 mA, 1 = 2 mA, 2 = 3 mA, 3 = 4 mA).
CK Oscillator Bias (0 = 0.25 mA, 1 = 0.35 mA, 2 = 0.53 mA, 3 = 0.85 mA).
ADC Amplifier Bias (0 = 2.4 mA, 1 = 3.2 mA, 2 = 4.0 mA, 3 = 4.8 mA).
0x02 (7:0)
8 0x00
TEST
Factory Test Mode.
AGC
0x03
(7)
(6:0)
10
7 0x3F
ATTEN
Apply 16 dB attenuation in the front end.
AGCG(14:8) AGC Gain Setting (7 MSBs of a 15-bit two’s-complement word).
0x04 (7:0)
8 0xFF
AGCG(7:0) AGC Gain Setting (8 LSBs of a 15-bit two’s-complement word).
Default corresponds to maximum gain.
0x05
(7:4)
(3:0)
40
40
AGCA
AGCD
AGC Attack Time Setting. Default yields 50 Hz raw loop bandwidth.
AGC Decay Time Setting. Default is decay time = attack time.
0x06
(7:4)
(3:0)
(2:0)
40
40
30
AGCO
AGCD
AGCR
AGC Overload Update Setting. Default is slowest update.
Fast AGC (Minimizes resistance seen between GCN and GCP).
AGC Enable/Reference Level (disabled, 3 dB, 6 dB, 9 dB, 12 dB, 15 dB below clip).
DECIMATION FACTOR
0x07 (3:0)
44
M Decimation Factor = 60 × (M + 1). Default is decimate-by-300.
LO SYNTHESIZER
0x08 (5:0)
6 0x00
LOR(13:8) Reference Frequency Divisor (6 MSBs of a 14-Bit Word).
0x09 (7:0)
0x0A
(7:5)
(4:0)
8 0x38
3 0x5
5 0x00
LOR(7:0)
LOA
LOB(12:8)
Reference Frequency Divisor (8 LSBs of a 14-Bit Word).
Default (56) Yields 300 kHz from fREF = 16.8 MHz.
“A” Counter (Prescaler Control Counter).
“B” Counter MSBs (5 MSBs of a 13-Bit Word).
Default LOA and LOB Values Yield 300 kHz from 73.35 MHz–2.25 MHz.
0x0B (7:0)
8 0x1D
LOB(7:0) “B” Counter LSBs (8 LSBs of a 13-Bit Word).
0x0C
(6)
(5)
(4:2)
(1:0)
10
10
30
20
LOF
LOINV
LOI
LOTM
Enable Fast Acquire.
Invert Charge Pump (0 = Pump_Up ⇒ IOUTL Sources Current).
Charge Pump Current in Normal Operation. IPUMP = (LOI + 1) × 0.625 mA.
Manual Control of LO Charge Pump (3 = Off, 2 = Down, 1 = Up, 0 = Normal).
0x0D (3:0)
4 0x0
LOFA(13:8) LO Fast Acquire Time Unit (4 MSBs of a 14-Bit Word).
0x0E (7:0)
8 0x04
LOFA(7:0) LO Fast Acquire Time Unit (8 LSBs of a 14-Bit Word).
CLOCK SYNTHESIZER
0x10 (5:0)
6 00
CKR(13:8) Reference Frequency Divisor (6 MSBs of a 14-Bit Word).
0x11 (7:0)
8 0x38
CKR(7:0)
Reference Frequency Divisor (8 LSBs of a 14-Bit Word).
Default Yields 300 kHz from fREF =16.8 MHz.
Min = 3, Max = 16383.
0x12 (4:0)
5 0x00
CKN(12:8) Synthesized Frequency Divisor (5 MSBs of a 13-Bit Word).
REV. 0
–5–
5 Page 
AD9870
The recommended setting for LOFA is LOR/16. Choosing a
larger value for LOFA will increase T. Thus, for a given phase
difference between the LO input and the fREF input, the instan-
taneous charge pump current will be less than that available for
a LOFA value of LOR/16. Similarly, a smaller value for LOFA
will decrease T, making more current available for the same
phase difference. In other words, a smaller value of LOFA will
enable the synthesizer to settle faster in response to a frequency
hop than will a large LOFA value. Care must be taken to choose
a value of LOFA which is large enough (values greater than four
recommended) to prevent the loop from oscillating back and
forth in response to a frequency hop.
Table V. SPI Registers Associated with LO Synthesizer
Address Bit
(Hex) Breakdown Width
0x00
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
(7:0)
(5:0)
(7:0)
(7:5)
(4:0)
(7:0)
(6)
(5)
(4:2)
(1:0)
(3:0)
(7:0)
8
6
8
3
5
8
1
1
3
2
4
8
Default Value Name
0xFF
0x00
0x38
0x5
0x00
0x1D
0
0
0
0
0x0
0x04
STBY
LOR(13:8)
LOR(7:0)
LOA
LOB(12:8
LOB(7:0)
LOF
LOINV
LOI
LOTM
LOFA(13:8)
LOFA(7:0)
CLOCK SYNTHESIZER
The clock synthesizer is a fully programmable integer-N PLL
capable of 2.2 kHz resolution at clock input frequencies up to
18 MHz and reference frequencies up to 25 MHz. It is similar
to the LO synthesizer described previously in Figure 4 with the
following exceptions:
• It does not include an 8/9 prescaler nor an A Counter.
• It includes a negative-resistance core which when used in
conjunction with an external varactor serves as the VCO.
The 14-bit reference counter and 13-bit N-divider counter can
be programmed via the following registers: CKR and CKN. The
charge pump current is programmable via the CKI register
from 0.625 mA to 5.0 mA using the following equation:
IPUMP = (CKI + 1) × 0.625 mA.
The fast acquire subcircuit of the charge pump is controlled by
the CKFA register in the same manner as the LO synthesizer is
controlled by the LOFA register. An on-chip lock detect func-
tion (enabled by the CKF bit) automatically increases the output
current for faster settling during channel changes. The synthe-
sizer may also be disabled using the CKOB standby bit located
in the STBY register.
LOOP
FILTER
RD
COSC
CVAR
LOSC
VDDC=3.0 V
RBIAS
0.1F
IOUTC
AD9870
CLKP
CLKN
VCM = VDDC – RBIAS ؋ IBIAS > 1.6V
fOSC > (2 ؋ LOSC ؋(CVARACTOR//COSC))–1/2
CLK OSC. BIAS
2
IBIAS = 0.25, 0.35,
0.53, OR 0.85 mA
Figure 6. External Loop Filter, Varactor and L-C Tank Are
Required to Realize a Complete Clock Synthesizer
The AD9870 clock synthesizer circuitry includes a negative-
resistance core so that only an external L-C tank circuit with a
varactor is needed to realize a voltage controlled oscillator (VCO).
Figure 6 shows the external components required to complete
the clock synthesizer along with the equivalent input of the CLK
input. The resonant frequency of the VCO is approximately deter-
mined by LOSC and the series equivalent capacitance of COSC and
CVAR. As a result, LOSC, COSC, and CVAR should be selected to
provide sufficient tuning range to ensure proper locking of the
clock synthesizer The bias, IBIAS, of the negative-resistance core
has four programmable settings. Lower equivalent Q of the L-C
tank circuit may require a higher bias setting of the negative-
resistance core to ensure proper oscillation. RBIAS should be
selected such that the common-mode voltage at CLKP and
CLKN is approximately 1.6 V. The synthesizer may be disabled
via the CK standby bit to allow the user to employ an external
synthesizer and/or VCO in place of those resident on the IC.
Table VI. SPI Registers Associated with CLK Synthesizer
Address
(Hex)
0x00
0x01
0x10
0x11
0x12
0x13
0x14
0x15
0x16
Bit
Breakdown Width
(7:0)
(3:2)
(5:0)
(7:0)
(4:0)
(7:0)
(6)
(5)
(4:2)
(1:0)
(3:0)
(7:0)
8
2
6
8
5
8
1
1
3
1
4
8
Default Value Name
0xFF
0
00
0x38
0x00
0x3C
0
0
0
0
0x0
0x04
STBY
CKOB
CKR(13:8)
CKR(7:0)
CKN(12:8)
CKN(7:0)
CKF
CKINV
CKI
CKTM
CKFA(13:8)
CKFA(7:0)
REV. 0
–11–
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD9870.PDF ] | |
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