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PDF AD9859 Data sheet ( Hoja de datos )
| Número de pieza | AD9859 | |
| Descripción | 400 MSPS/ 10-Bit/ 1.8 V CMOS Direct Digital Synthesizer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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400 MSPS, 10-Bit, 1.8 V CMOS
Direct Digital Synthesizer
AD9859
FEATURES
400 MSPS internal clock speed
Integrated 10-bit DAC
32-bit tuning word
Phase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output)
Excellent dynamic performance
>75 dB SFDR @ 160 MHz (±100 kHz offset) AOUT
Serial I/O control
1.8 V power supply
Software and hardware controlled power-down
48-lead TQFP/EP package
Support for 5 V input levels on most digital inputs
PLL REFCLK multiplier (4× to 20×)
Internal oscillator; can be driven by a single crystal
Phase modulation capability
Multichip synchronization
APPLICATIONS
Agile LO frequency synthesis
Programmable clock generators
Test and measurement equipment
Commercial and amateur radio exciter
GENERAL DESCRIPTION
The AD9859 is a direct digital synthesizer (DDS) featuring a
10-bit DAC operating at up to 400 MSPS. The AD9859 uses
advanced DDS technology, coupled with an internal high speed,
high performance DAC to form a digitally programmable,
complete high frequency synthesizer capable of generating a
frequency-agile analog output sinusoidal waveform at up to
200 MHz. The AD9859 is designed to provide fast frequency
hopping and fine tuning resolution (32-bit frequency tuning
word). The frequency tuning and control words are loaded into
the AD9859 via a serial I/O port.
The AD9859 is specified to operate over the extended industrial
temperature range of –40°C to +105°C
FUNCTIONAL BLOCK DIAGRAM
I/O UPDATE
SYNC_CLK
REFCLK
REFCLK
DDS CORE
PHASE
ACCUMULATOR
Z–1
32
PHASE
OFFSET
19
14
Z–1
COS(X)
AD9859
10 DAC
SYSTEM
10 CLOCK
32
14
0
M
U
X
SYNC
OSCILLATOR/BUFFER
ENABLE
4×–20×
CLOCK
MULTIPLIER
TIMING AND CONTROL LOGIC
÷ 4 CONTROL REGISTERS
M
U
X
SYSTEM
CLOCK
DAC_RSET
IOUT
IOUT
SYNC_IN
OSK
PWRDWNCTL
CRYSTAL OUT
I/O PORT
Figure 1.
RESET
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Maximum Junction Temperature
DVDD_I/O (Pin 43)
AVDD, DVDD
Digital Input Voltage (DVDD_I/O = 3.3 V)
Digital Input Voltage (DVDD_I/O = 1.8 V)
Digital Output Current
Storage Temperature
Operating Temperature
Lead Temperature (10 sec Soldering)
θJA
θJC
Rating
150°C
4V
2V
–0.7 V to +5.25 V
–0.7 V to +2.2 V
5 mA
–65°C to +150°C
–40°C to +105°C
300°C
38°C/W
15°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at these or any
other conditions above those indicated in the operational sec-
tion of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
DIGITAL
INPUTS
DVDD_I/O
INPUT
DAC OUTPUTS
IOUT
IOUT
AVOID OVERDRIVING
DIGITAL INPUTS.
FORWARD BIASING
ESD DIODES MAY
COUPLE DIGITAL NOISE
ONTO POWER PINS.
MUST TERMINATE
OUTPUTS TO AVDD. DO
NOT EXCEED THE
OUTPUT VOLTAGE
COMPLIANCE RATING.
Figure 2. Equivalent Input and Output Circuits
AD9859
Rev. 0 | Page 5 of 24
5 Page 
AD9859
THEORY OF OPERATION
COMPONENT BLOCKS
DDS Core
The output frequency (fO) of the DDS is a function of the
frequency of the system clock (SYSCLK), the value of the
frequency tuning word (FTW), and the capacity of the accumu-
lator (232 in this case). The exact relationship is given below with
fS defined as the frequency of SYSCLK.
fO = (FTW )( fS )/232 with 0 ≤ FTW ≤ 231
( ( ))fO = fS × 1– FTW /232 with 231 < FTW < 232 –1
The value at the output of the phase accumulator is translated to
an amplitude value via the COS(x) functional block and routed
to the DAC.
In certain applications, it is desirable to force the output signal
to zero phase. Simply setting the FTW to 0 does not accomplish
this; it only results in the DDS core holding its current phase
value. Thus, a control bit is required to force the phase accumu-
lator output to zero.
At power-up, the clear phase accumulator bit is set to Logic 1,
but the buffer memory for this bit is cleared (Logic 0). There-
fore, upon power-up, the phase accumulator remains clear until
the first I/O UPDATE is issued.
Phase-Locked Loop (PLL)
The PLL allows multiplication of the REFCLK frequency. Con-
trol of the PLL is accomplished by programming the 5-bit
REFCLK multiplier portion of Control Function Register No. 2,
Bits <7:3>.
When programmed for values ranging from 0x04 to 0x14
(4 decimal to 20 decimal), the PLL multiplies the REFCLK input
frequency by the corresponding decimal value. However, the
maximum output frequency of the PLL is restricted to
400 MHz. Whenever the PLL value is changed, the user should
be aware that time must be allocated to allow the PLL to lock
(approximately 1 ms).
The PLL is bypassed by programming a value outside the range
of 4 to 20 (decimal). When bypassed, the PLL is shut down to
conserve power.
Clock Input
The AD9859 supports various clock methodologies. Support for
differential or single-ended input clocks and enabling of an
on-chip oscillator and/or a phase-locked loop (PLL) multiplier
are all controlled via user programmable bits. The AD9859 may
be configured in one of six operating modes to generate the
system clock. The modes are configured using the CLKMODE-
SELECT pin, CFR1<4>, and CFR2<7:3>. Connecting the exter-
nal pin CLKMODESELECT to Logic High enables the on-chip
crystal oscillator circuit. With the on-chip oscillator enabled,
users of the AD9859 connect an external crystal to the REFCLK
and REFCLKB inputs to produce a low frequency reference
clock in the range of 20 MHz to 30 MHz. The signal generated
by the oscillator is buffered before it is delivered to the rest of
the chip. This buffered signal is available via the CRYSTAL
OUT pin. Bit CFR1<4> can be used to enable or disable the
buffer, turning on or off the system clock. The oscillator itself is
not powered down in order to avoid long startup times associ-
ated with turning on a crystal oscillator. Writing CFR2<9> to
Logic High enables the crystal oscillator output buffer. Logic
Low at CFR2<9> disables the oscillator output buffer.
Connecting CLKMODESELECT to Logic Low disables the
on-chip oscillator and the oscillator output buffer. With the
oscillator disabled, an external oscillator must provide the
REFCLK and/or REFCLKB signals. For differential operation,
these pins are driven with complementary signals. For single-
ended operation, a 0.1 µF capacitor should be connected
between the unused pin and the analog power supply. With the
capacitor in place, the clock input pin bias voltage is 1.35 V. In
addition, the PLL may be used to multiply the reference
frequency by an integer value in the range of 4 to 20. Table 4
summarizes the clock modes of operation. Note that the PLL
multiplier is controlled via the CFR2<7:3> bits, independent of
the CFR1<4> bit.
Table 4. Clock Input Modes of Operation
CFR1<4> CLKMODESELECT
CFR2<7:3>
Low High
3 < M < 21
Low High
M < 4 or M > 20
Low Low
3 < M < 21
Low Low
M < 4 or M > 20
High
X
X
Oscillator Enabled?
Yes
Yes
No
No
No
System Clock
FCLK = FOSC × M
FCLK = FOSC
FCLK = FOSC × M
FCLK = FOSC
FCLK = 0
Frequency Range (MHz)
80 < FCLK < 400
20 < FCLK < 30
80 < FCLK < 400
10 < FCLK < 400
N/A
Rev. 0 | Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD9859.PDF ] | |
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