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PDF AD9857 Data sheet ( Hoja de datos )
| Número de pieza | AD9857 | |
| Descripción | CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD9857 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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CMOS 200 MSPS 14-Bit
Quadrature Digital Upconverter
AD9857
FEATURES
200 MHz internal clock rate
14-bit data path
Excellent dynamic performance:
80 dB SFDR @ 65 MHz (±100 kHz) AOUT
4× to 20× programmable reference clock multiplier
Reference clock multiplier PLL lock detect indicator
Internal 32-bit quadrature DDS
FSK capability
8-bit output amplitude control
Single-pin power-down function
Four programmable, pin-selectable signal profiles
SIN(x)/x correction (inverse SINC function)
Simplified control interface
10 MHz serial, 2-wire or 3-wire SPI®-compatible
3.3 V single supply
Single-ended or differential input reference clock
80-lead LQFP surface-mount packaging
Three modes of operation:
Quadrature modulator mode
Single-tone mode
Interpolating DAC mode
APPLICATIONS
HFC data, telephony, and video modems
Wireless base station
Agile, LO frequency synthesis
Broadband communications
PARALLEL
DATA IN
(14-BIT)
INVERSE
CIC FILTER
I
14
INV
14 CIC
Q
FUNCTIONAL BLOCK DIAGRAM
FIXED
INTER-
POLATOR PROGRAMMABLE
INTERPOLATOR
(4 )
CIC
(2 - 63 )
QUADRATURE
MODULATOR
INVERSE
SINC
FILTER
DDS
CORE
CONTROL REGISTERS
TUNING
WORD 32
TIMING AND CONTROL
AD9857
14
8
14-BIT
DAC
OUTPUT
SCALE
VALUE
DAC_RSET
IOUT
IOUT
POWER- PROFILE
DOWN SELECT
LOGIC LOGIC
CLOCK
MULTIPLIER
(4 – 20 )
MODE
CONTROL
REFCLK
REFCLK
PDCLK/ TxENABLE RESET CIC
SERIAL
FUD
OVERFLOW PORT
DIGITAL PS1 PS0
POWER-
DOWN
Figure 1.
PLL
LOCK
CLOCK
INPUT
MODE
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
AD9857
GENERAL DESCRIPTION
The AD9857 integrates a high speed direct digital synthesizer
(DDS), a high performance, high speed, 14-bit digital-to-analog
converter (DAC), clock multiplier circuitry, digital filters, and
other DSP functions onto a single chip, to form a complete
quadrature digital upconverter device. The AD9857 is intended
to function as a universal I/Q modulator and agile upconverter,
single-tone DDS, or interpolating DAC for communications
applications, where cost, size, power dissipation, and dynamic
performance are critical attributes.
The AD9857 offers enhanced performance over the industry-
standard AD9856, as well as providing additional features.
The AD9857 is available in a space-saving, surface-mount
package and is specified to operate over the extended industrial
temperature range of −40°C to +85°C.
Rev. C | Page 4 of 40
5 Page 
AD9857
Pin Number
35, 37, 38, 43,
48, 54, 58, 64
36, 39, 40, 42,
44, 47, 53, 56,
59, 61, 65
45
46
49
50
55
60
62
63
66
67
68
69
79
80
Mnemonic
AVDD
AGND
IOUT
IOUT
DAC_BP
DAC_RSET
PLL_FILTER
DIFFCLKEN
REFCLK
REFCLK
DPD
RESET
PLL_LOCK
CIC_OVRFL
PDCLK/FUD
TxENABLE
I/O Function
3.3 V Analog Power pin(s).
Analog Ground pin(s).
O DAC Output pin. Normal DAC output current (analog).
O DAC Complementary Output pin. Complementary DAC output current (analog).
DAC Reference Bypass. Typically not used.
I DAC Current Set pin. Sets DAC reference current.
O PLL Filter. R-C network for PLL filter.
I Clock Mode Select pin. A logic high on this pin selects DIFFERENTIAL REFCLK input mode. A logic
low selects the SINGLE-ENDED REFCLK input mode.
I Reference Clock pin. In single-ended clock mode, this pin is the Reference Clock input. In differential
clock mode, this pin is the positive clock input.
I Inverted Reference Clock pin. In differential clock mode, this pin is the negative clock input.
I Digital Power-Down pin. Assertion of this pin shuts down the digital sections of the device to
conserve power. However, if selected, the PLL remains operational.
I Hardware RESET pin. An active high input that forces the device into a predefined state.
O PLL Lock pin. Active high output signifying, in real time, when PLL is in lock state.
O CIC Overflow pin. Activity on this pin indicates that the CIC Filters are in “overflow” state. This pin is
typically low unless a CIC overflow occurs.
I/O Parallel Data Clock/Frequency Update pin. When not in single-tone mode, this pin is an output
signal that should be used as a clock to synchronize the acceptance of the 14-bit parallel
data-words on Pins D13–D0. In single-tone mode, this pin is an input signal that synchronizes the
transfer of a changed frequency tuning word (FTW) in the active profile (PSx) to the accumulator
(FUD = frequency update signal). When profiles are changed by means of the PS–PS1 pins, the FUD
does not have to be asserted to make the FTW active.
I When TxENABLE is asserted, the device processes the data through the I and Q data pathways;
otherwise 0s are internally substituted for the I and Q data entering the signal path. The first data
word accepted when the TxENABLE is asserted high is treated as I data, the next data word is Q data,
and so forth.
Rev. C | Page 10 of 40
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9857.PDF ] | |
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