PDF AD9856 Data sheet ( Hoja de datos )

Número de pieza	AD9856
Descripción	CMOS 200 MHz Quadrature Digital Upconverter
Fabricantes	Analog Devices
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FEATURES Universal low cost modulator solution for communications applications DC to 80 MHz output bandwidth Integrated 12-bit D/A converter Programmable sample rate interpolation filter Programmable reference clock multiplier Internal SIN(x)/x compensation filter >52 dB SFDR @ 40 MHz AOUT >48 dB SFDR @ 70 MHz AOUT >80 dB narrow-band SFDR @ 70 MHz AOUT +3 V single-supply operation Space-saving surface-mount packaging Bidirectional control bus interface Supports burst and continuous Tx modes Single-tone mode for frequency synthesis applications Four programmable, pin-selectable, modulator profiles Direct interface to AD8320/AD8321 PGA cable driver CMOS 200 MHz Quadrature Digital Upconverter AD9856 APPLICATIONS HFC data, telephony, and video modems Wireless and satellite communications Cellular base stations GENERAL DESCRIPTION The AD9856 integrates a high speed, direct digital synthesizer (DDS), a high performance, high speed, 12-bit digital-to-analog converter (DAC), clock multiplier circuitry, digital filters, and other DSP functions on a single chip to form a complete quadrature digital upconverter device. The AD9856 is intended to function as a universal I/Q modulator and agile upconverter for communications applications where cost, size, power dissipation, and dynamic performance are critical attributes. The AD9856 is available in a space-saving surface-mount package, and is specified to operate over the extended industrial temperature range of −40°C to +85°C. COMPLEX DATA IN TxENABLE (I /Q SYNC) FUNCTIONAL BLOCK DIAGRAM 12 4 × TO 8 × 12 SELECTABLE INTERPOLATING HALFBANDS 12 4 × TO 8 × SELECTABLE 12 INTERPOLATING HALFBANDS 4 × TO 20 × PROG. CLOCK MULTIPLIER 2 × TO 63 × 12 SELECTABLE INTERPOLATOR 12 12 2 × TO 63 × SELECTABLE INTERPOLATOR 12 12 12 12 SINE COSINE DDS AND CONTROL FUNCTIONS AD9856 INV 12 12-BIT SINC DAC DC-80 MHz OUTPUT DAC RSET SPI INTERFACE TO AD8320/AD8321 PROGRAMMABLE CABLE DRIVER AMPLIFIER REFERENCE CLOCK IN PROFILE SELECT 1–2 PROFILE SELECT 3–4 MASTER RESET BIDIRECTIONAL SPI CONTROL INTERFACE: 32-BIT FREQUENCY TUNING WORD FREQUENCY UPDATE INTERPOLATION FILTER RATE REFERENCE CLOCK MULTIPLIER RATE SPECTRAL PHASE INVERSION ENABLE CABLE DRIVER AMPLIFIER CONTROL Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved. 1 page AD9856 Parameter TIMING CHARACTERISTICS Serial Control Bus Maximum Frequency Minimum Clock Pulse Width High (tPWH) Minimum Clock Pulse Width Low (tPWL) Maximum Clock Rise/Fall Time Minimum Data Setup Time (tDS) Minimum Data Hold Time (tDH) Maximum Data Valid Time (tDV) Wake-Up Time2 Minimum RESET Pulse Width High (tRH) CMOS LOGIC INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance CMOS LOGIC OUTPUTS (1 mA LOAD) Logic 1 Voltage Logic 0 Voltage POWER SUPPLY +VS Current Full Operating Conditions3 Burst Operation (25%) Single-Tone Mode 160 MHz Clock 120 MHz Clock Power-Down Mode 2 Assuming 1.3 kΩ and 0.01 µF loop filter components. 3 Assuming 1.3 kW and 0.01 mF loop filter components. Temp Test Level Min Typ Max Unit Full IV Full IV Full IV Full IV Full IV Full IV Full IV Full IV Full IV 25°C I 25°C I 25°C I 25°C I 25°C V 25°C I 25°C I 30 30 25 0 30 5 2.6 3 2.7 10 MHz ns ns 1 ms ns ns ns 1 ms REFCLK cycles V 0.4 V 12 µA 12 µA pF mA 0.4 mA 25°C I 25°C I 25°C I 25°C I 25°C I 25°C I 530 mA 450 mA 495 mA 445 mA 345 mA 2 mA Rev. C \| Page 4 of 36 5 Page AD9856 TYPICAL NARROW-BAND SFDR SPECTRAL PLOTS REF LVL –5dBm 0 –10 RBW 100Hz VBW 100Hz SWT 50s RF ATT 20dB UNIT dB A –20 –30 1AP –40 –50 –60 –70 –80 –90 –100 CENTER 70.1MHz 10kHz/ SPAN 100kHz Figure 11. 70.1 MHz Narrow-Band SFDR, 10 MHz External Clock with REFCLK Multiplier = 20× REF LVL –5dBm 0 –12 RBW 100Hz VBW 100Hz SWT 50s RF ATT 20dB UNIT dB A –24 –36 1AP –48 –60 –72 –84 –96 –108 –120 CENTER 70.1MHz 10kHz/ SPAN 100kHz Figure 12. 70.1 MHz Narrow-Band SFDR, 200 MHz External Clock with REFCLK Multiplier Disabled TYPICAL PHASE NOISE SPECTRAL PLOTS REF LVL 0dBm 0 FXD –2.248dBm –12 RBW 30Hz VBW 30Hz SWT 28s RF ATT 30dB UNIT dB A –24 –36 1AP –48 –60 –72 –84 –96 –108 –120 CENTER 40.1MHz FXD 500Hz/ SPAN 5kHz Figure 13. 40.1 MHz Output, 10 MHz External Clock with REFCLK Multiplier = 20× REF LVL 0dBm 0 FXD –2.248dBm –12 RBW 30Hz VBW 30Hz SWT 28s RF ATT 30dB UNIT dB A –24 –36 1AP –48 –60 –72 –84 –96 –108 –120 CENTER 40.1MHz FXD 500Hz/ SPAN 5kHz Figure 14. 40.1 MHz Output, 200 MHz External Clock with REFCLK Multiplier Disabled Rev. C \| Page 10 of 36 11 Page

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