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PDF AD9854 Data sheet ( Hoja de datos )
| Número de pieza | AD9854 | |
| Descripción | CMOS 300 MHz Quadrature Complete-DDS | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD9854 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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CMOS 300 MSPS Quadrature
Complete DDS
AD9854
FEATURES
300 MHz internal clock rate
FSK, BPSK, PSK, chirp, AM operation
Dual integrated 12-bit digital-to-analog converters (DACs)
Ultrahigh speed comparator, 3 ps rms jitter
Excellent dynamic performance
80 dB SFDR at 100 MHz (±1 MHz) AOUT
4× to 20× programmable reference clock multiplier
Dual 48-bit programmable frequency registers
Dual 14-bit programmable phase offset registers
12-bit programmable amplitude modulation and
on/off output shaped keying function
Single-pin FSK and BPSK data interfaces
PSK capability via input/output interface
Linear or nonlinear FM chirp functions with single-pin
frequency hold function
Frequency-ramped FSK
<25 ps rms total jitter in clock generator mode
Automatic bidirectional frequency sweeping
Sin(x)/x correction
Simplified control interfaces
10 MHz serial 2- or 3-wire SPI compatible
100 MHz parallel 8-bit programming
3.3 V single supply
Multiple power-down functions
Single-ended or differential input reference clock
Small, 80-lead LQFP or TQFP with exposed pad
APPLICATIONS
Agile, quadrature LO frequency synthesis
Programmable clock generators
FM chirp source for radar and scanning systems
Test and measurement equipment
Commercial and amateur RF exciters
FUNCTIONAL BLOCK DIAGRAM
REFERENCE
CLOCK IN
DIFF/SINGLE
SELECT
FSK/BPSK/HOLD
DATA IN
REF
CLK
BUFFER
SYSTEM CLOCK
4× TO 20×
REF CLK
MULTIPLIER
48 48
SYSTEM
CLOCK
MUX
48
3
MUX
DELTA
FREQUENCY
RATE TIMER
MUX
DDS CORE
17 17
14
MUX
12
I
12
Q
INV DIGITAL MULTIPLIERS
SINC
12
FILTER
12-BIT
I
DAC
INV
SINC
FILTER
SYSTEM
CLOCK
12
12-BIT
Q DAC OR
CONTROL
DAC
SYSTEM
CLOCK
12 12
PROGRAMMABLE
AMPLITUDE AND
RATE CONTROL
ANALOG
OUT
DAC RSET
ANALOG
OUT
ANALOG
IN
2 48 SYSTEM 48
CLOCK
DELTA
FREQUENCY
WORD
FREQUENCY
TUNING
WORD 1
48 14
14 12 12
FREQUENCY FIRST 14-BIT SECOND 14-BIT I AND Q 12-BIT 12-BIT DC
TUNING PHASE/OFFSET PHASE/OFFSET AM MODULATION CONTROL
WORD 2
WORD
WORD
COMPARATOR
CLOCK
OUT
BIDIRECTIONAL
INTERNAL/EXTERNAL
I/O UPDATE CLOCK
MODE SELECT
SYSTEM
CLOCK
INT
CK Q
D
EXT
PROGRAMMING REGISTERS
÷2
SYSTEM
CLOCK
AD9854
INTERNAL
PROGRAMMABLE
UPDATE CLOCK
BUS
I/O PORT BUFFERS
OSK
GND
+VS
READ
WRITE SERIAL/
PARALLEL
SELECT
Figure 1.
6-BIT ADDRESS
OR SERIAL
PROGRAMMING
LINES
8-BIT
PARALLEL
LOAD
MASTER
RESET
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2007 Analog Devices, Inc. All rights reserved.
1 page  
AD9854
SPECIFICATIONS
VS = 3.3 V ± 5%, RSET = 3.9 kΩ, external reference clock frequency = 30 MHz with REFCLK multiplier enabled at 10× for AD9854ASVZ,
external reference clock frequency = 20 MHz with REFCLK multiplier enabled at 10× for AD9854ASTZ, unless otherwise noted.
Table 1.
Parameter
REFERENCE CLOCK INPUT CHARACTERISTICS1
Internal System Clock Frequency Range
REFCLK Multiplier Enabled
REFCLK Multiplier Disabled
External Reference Clock Frequency Range
REFCLK Multiplier Enabled
REFCLK Multiplier Disabled
Duty Cycle
Input Capacitance
Input Impedance
Differential Mode Common-Mode Voltage Range
Minimum Signal Amplitude2
Common-Mode Range
VIH (Single-Ended Mode)
VIL (Single-Ended Mode)
DAC STATIC OUTPUT CHARACTERISTICS
Output Update Speed
Resolution
I and Q Full-Scale Output Current
I and Q DAC DC Gain Imbalance3
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
Output Impedance
Voltage Compliance Range
DAC DYNAMIC OUTPUT CHARACTERISTICS
I and Q DAC Quadrature Phase Error
DAC Wideband SFDR
1 MHz to 20 MHz AOUT
20 MHz to 40 MHz AOUT
40 MHz to 60 MHz AOUT
60 MHz to 80 MHz AOUT
80 MHz to 100 MHz AOUT
100 MHz to 120 MHz AOUT
DAC Narrow-Band SFDR
10 MHz AOUT (±1 MHz)
10 MHz AOUT (±250 kHz)
10 MHz AOUT (±50 kHz)
41 MHz AOUT (±1 MHz)
41 MHz AOUT (±250 kHz)
41 MHz AOUT (±50 kHz)
119 MHz AOUT (±1 MHz)
119 MHz AOUT (±250 kHz)
119 MHz AOUT (±50 kHz)
Test AD9854ASVZ
AD9854ASTZ
Temp Level Min Typ Max Min Typ Max Unit
Full VI
Full VI
Full VI
Full VI
25°C IV
25°C IV
25°C IV
25°C IV
25°C IV
25°C IV
25°C IV
Full I
25°C IV
25°C IV
25°C I
25°C I
25°C I
25°C I
25°C I
25°C IV
25°C I
25°C IV
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
20 300 20 200 MHz
DC 300 DC 200 MHz
5 75 5 50 MHz
DC 300 DC 200 MHz
45 50 55 45 50 55 %
3 3 pF
100 100 kΩ
400
1.6 1.75
2.3
1.9
1
400
1.6 1.75
2.3
1.9
1
mV p-p
V
V
V
300 200 MSPS
12 12 Bits
5 10 20 5 10 20 mA
−0.5 +0.15 +0.5 −0.5 +0.15 +0.5 dB
−6 +2.25 −6 +2.25 % FS
2 2 μA
0.3 1.25
0.3 1.25 LSB
0.6 1.66
0.6 1.66 LSB
100 100 kΩ
−0.5 +1.0 −0.5 +1.0 V
0.2 1
0.2 1
Degrees
58 58 dBc
56 56 dBc
52 52 dBc
48 48 dBc
48 48 dBc
48 48 dBc
83 83 dBc
83 83 dBc
91 91 dBc
82 82 dBc
84 84 dBc
89 89 dBc
71 71 dBc
77 77 dBc
83 83 dBc
Rev. E | Page 5 of 52
5 Page 
AVDD
AVDD
AD9854
DVDD
AVDD
DIGITAL
IN
IOUT IOUTB
MUST TERMINATE OUTPUTS
FOR CURRENT FLOW. DO
NOT EXCEED THE OUTPUT
VOLTAGE COMPLIANCE RATING.
A. DAC OUTPUTS
COMPARATOR
OUT
VINP/
VINN
B. COMPARATOR OUTPUT
C. COMPARATOR INPUT
Figure 3. Equivalent Input and Output Circuits
AVOID OVERDRIVING
DIGITAL INPUTS. FORWARD
BIASING ESD DIODES MAY
COUPLE DIGITAL NOISE
ONTO POWER PINS.
D. DIGITAL INPUTS
Rev. E | Page 11 of 52
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9854.PDF ] | |
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