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PDF AD9853 Data sheet ( Hoja de datos )
| Número de pieza | AD9853 | |
| Descripción | Programmable Digital OPSK/16-QAM Modulator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Programmable Digital
QPSK/16-QAM Modulator
AD9853
FEATURES
GENERAL DESCRIPTION
Universal Low Cost Solution for HFC Network
The AD9853 integrates a high speed direct-digital synthesizer
Return-Channel TX Function: 5 MHz–42 MHz/
(DDS), a high performance, high speed digital-to-analog con-
5 MHz–65 MHz
verter (DAC), digital filters and other DSP functions onto a
165 MHz Internal Reference Clock Capability
single chip, to form a complete and flexible digital modulator
Includes Programmable Pulse-Shaping FIR Filters and
device. The AD9853 is intended to function as a modulator in
Programmable Interpolating Filters
network applications such as interactive HFC, WLAN and
FSK/QPSK/DQPSK/16-QAM/D16-QAM Modulation
MMDS, where cost, size, power dissipation, functional integra-
Formats
tion and dynamic performance are critical attributes.
6؋ Internal Reference Clock Multiplier
The AD9853 is fabricated on an advanced CMOS process and
Integrated Reed-Solomon FEC Function
it sets a new standard for CMOS digital modulator performance.
Programmable Randomizer/Preamble Function
The device is loaded with programmable functionality and
Supports Interoperable Cable Modem Standards
Internal SINx/x Compensation
>50 dB SFDR @ 42 MHz Output Frequency (Single Tone)
Controlled Burst Mode Operation
+3.3 V to +5 V Single Supply Operation
Low Power: 750 mW @ Full Clock Speed (3.3 V Supply)
Space Saving Surface Mount Packaging
OAPPLICATIONS
BHFC Data, Telephony and Video Modems
Wireless LAN
provides a direct interface port to the AD8320, digitally-
programmable cable driver amplifier. The AD9853/AD8320
chipset forms a highly integrated, low power, small footprint
and cost-effective solution for the HFC return-path requirement
and other more general purpose modulator applications.
The AD9853 is available in a space saving surface mount pack-
age and is specified to operate over the extended industrial
temperature range of –40°C to +85°C.
SOFUNCTIONAL BLOCK DIAGRAM
LESERIAL
TEDATAIN
R-S
FEC
DATA
XOR DELAY
& MUX
ENCODER:
FSK
QPSK
DQPSK
16-QAM
D16-QAM
FIR
FILTER
INTERPOLATION
FILTER
FIR INTERPOLATION
AD9853
10
INV
SYNC
FILTER
10-BIT
10 DAC
AOUT
TO LP FILTER
AND AD8320
RANDOMIZER
PREAMBLE
INSERTION
FILTER
FILTER
GAIN
CONTROL TO
CABLE DRIVER
AMPLIFER
SINE
COSINE
DRIVER AMP
DDS
CLOCK
6؋
CONTROL FUNCTIONS
REF CLOCK IN
FEC TXENABLE RESET
ENABLE/
DISABLE
SERIAL CONTROL BUS:
32-BIT OUTPUT FREQUENCY TUNING WORD
INPUT DATA RATE/MODULATION FORMAT
FEC/RANDOMIZER/PREAMBLE ENABLE/CONFIGURATION
FIR FILTER COEFFICIENTS
REF CLOCK MULTIPLIER ENABLE
I/Q PHASE INVERT
SLEEP MODE
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1 page  
AD9853
Table I. Modulator Function Description
Modulation Encoding Format
FSK*, QPSK, DQPSK, 16-QAM, D16-QAM, Selectable via Control Bus
Output Carrier Frequency Range
DC – 63 MHz with +3.3 V Supply Voltage
DC – 84 MHz with +5 V Supply Voltage
Serial Input Data Rate
Evenly Divisible Fraction of Reference Clock
Pulse-Shaping FIR Filter
41 Tap, Linear Phase, 10-Bit Coefficients Fully Programmable via Control Bus
Interpolation Range
Interpolation Rate = (4/M) × (ICIC1) × (ICIC2) where: M = 2 for QPSK, M = 4 for 16-QAM
Minimum and Maximum Rates
Minimum Interpolation Rate—QPSK = 2 × 3 × 2 = 12
16-QAM = 1 × 4 × 3 = 12
Maximum Interpolation Rate—QPSK = 2 × 31 × 63 = 3906
16-QAM = 1 × 31 × 63 = 1953
These are the minimum and maximum interpolation ratios from the input data rate to the
system clock. The interpolation range is a function of the fixed interpolation factor of four
in the FIR filters, the programmed CIC filter interpolation rates (ICIC1, ICIC2), as well
Maximum Reference Clock Frequency
6× REFCLK
R-S FEC
OBSOLETEI/Q Channel Spectrum
as system timing constraints.
+3.3 V Supply: 21 MHz with 6× REFCLK enabled, 126 MHz with 6× REFCLK disabled
+5 V Supply: 28 MHz with 6× REFCLK enabled, 168 MHz with 6× REFCLK disabled
Fixed 6× reference clock multiplier, enable/disable control via control bus
Enable/disable via control bus and dedicated control pin. Control pin enable/disable function:
Logic “1” = Enable
Logic “0” = Disable
Primitive Polynomial: p(x) = x8 + x4 + x3 + x2 + 1
Code Generator Polynomial: g(x) = (x + α0)(x + α1)(x + α2) . . . (x + α2t –1)
Selectable via Control Bus
t = 0–10 (Programmable)
Codeword Length (N) = 255 max (Programmable)
N = K + 2 t (K Range = 16 ≤ K ≤ 255 – 2 t)
FEC/Randomizer can be transposed in signal chain via control bus.
I × COS + Q × SIN (default) or I × COS – Q × SIN, selectable via control bus.
Preamble Insertion
0–96 Bits, Programmable Length and Content
Randomizer
Enable/Disable Control via Control Bus
Generating Polynomial:
x6 + x5 + 1, Programmable Seed (Davic/DVB-Compliant)
or
x15 + x14 + 1, Programmable Seed (DOCSIS-Compliant)
Randomizer and FEC blocks can be transposed in signal chain, via control bus.
*In FSK mode, F0:F1 are direct DDS Cosine output. The two interpolator stages of the AD9853 are not used in the FSK mode and should be programmed for
maximum interpolation rates to reduce unnecessary current consumption. This means that Interpolator #1 should be set to a decimal value of 31, and Interpolator
#2 should be set to decimal value of 63. This is easily accomplished by programming Registers 12 and 13 (hex) with the values of FF (hex).
REV. C
–5–
5 Page 
AD9853
95 0.80
BIT RATE >2Mb/s
CLK = 122.88 MHz
85 VCC = +5V
0.75 VCC = +3.3V
CONTINUOUS MODE
CONTINUOUS MODE
75 0.70
65 0.65
55 0.60
45
110 115 120 125 130 135 140 145 150 155 160 165 170
MAX CLOCK RATE – MHz
Figure 20. Max CLK Rate vs. Ambient Temperature
(To Ensure Max Junction Temp is Not Exceeded)
0.55
0 12 3 456
BIT RATE – Mb/s
Figure 23. PWR Consumption vs. Bit Rate
2.6
2.4
VCC = +5.0V
O2.2
B2.0
S1.8
CLK = 165MHz
CONTINUOUS MODE
O1.6
L1.4 VCC = +4.0V
E1.2
TE0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
2.5
CLK = 165MHz
2.4
VCC = +5.0V
BIT RATE = 3.4Mb/s
2.3
2.2
2.1
2.0
1.9
0
20 40
60
80 100
BIT RATE – Mb/s
BURST MODE DUTY CYCLE – %
Figure 21. Power Consumption vs. Bit Rate
Figure 24. Power Consumption vs. Burst Duty Cycle
–40
AOUT = 42MHz
AOUT = 32MHz
–45
–50
AOUT = 22MHz
–55 AOUT = 12MHz
CLK = 122.88 MHz
VCC = +3.3V
–60
5.12
2.56
1.28
BIT RATE – Mb/s
0.64
Figure 22. Spurious Emission vs. Bit Rate vs. AOUT
–40
AOUT = 65MHz
–42
–44
AOUT = 40MHz
–46
–48
AOUT = 20MHz
–50
CLK = 165MHz
VCC = +4.0V TO +5.0V
–52
3.5 1.75 0.88
BIT RATE – Mb/s
0.44
Figure 25. Spurious Emission vs. Bit Rate vs. AOUT
REV. C
–11–
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9853.PDF ] | |
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