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PDF AD9851 Data sheet ( Hoja de datos )
| Número de pieza | AD9851 | |
| Descripción | CMOS 180 MHz DDS/DAC Synthesizer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
180 MHz Clock Rate with Selectable 6 Reference Clock
Multiplier
On-Chip High Performance 10-Bit DAC and High Speed
Comparator with Hysteresis
SFDR >43 dB @ 70 MHz AOUT
32-Bit Frequency Tuning Word
Simplified Control Interface: Parallel or Serial
Asynchronous Loading Format
5-Bit Phase Modulation and Offset Capability
Comparator Jitter <80 ps p-p @ 20 MHz
2.7 V to 5.25 V Single-Supply Operation
Low Power: 555 mW @ 180 MHz
Power-Down Function, 4 mW @ 2.7 V
Ultrasmall 28-Lead SSOP Packaging
APPLICATIONS
Frequency/Phase-Agile Sine Wave Synthesis
Clock Recovery and Locking Circuitry for Digital
Communications
Digitally Controlled ADC Encode Generator
Agile Local Oscillator Applications in Communications
Quadrature Oscillator
CW, AM, FM, FSK, MSK Mode Transmitter
CMOS 180 MHz
DDS/DAC Synthesizer
AD9851
FUNCTIONAL BLOCK DIAGRAM
+VS GND
AD9851
REF
CLOCK IN
MASTER
RESET
FREQUENCY
UPDATE/DATA
REGISTER
RESET
WORD LOAD
CLOCK
6 REFCLK
MULTIPLIER
HIGH SPEED
DDS
32-BIT
TUNING
WORD
PHASE
AND
CONTROL
WORDS
FREQUENCY/PHASE
DATA REGISTER
DATA INPUT REGISTER
SERIAL
LOAD
PARALLEL
LOAD
10-BIT
DAC
COMPARATOR
DAC RSET
ANALOG
OUT
ANALOG
IN
CLOCK OUT
CLOCK OUT
1 BIT
40 LOADS
8 BITS
5 LOADS
FREQUENCY, PHASE
AND CONTROL DATA INPUT
GENERAL DESCRIPTION
The AD9851 is a highly integrated device that uses advanced
DDS technology, coupled with an internal high speed, high
performance D/A converter, and comparator, to form a digitally
programmable frequency synthesizer and clock generator func-
tion. When referenced to an accurate clock source, the AD9851
generates a stable frequency and phase-programmable digitized
analog output sine wave. This sine wave can be used directly as
a frequency source, or internally converted to a square wave for
agile-clock generator applications. The AD9851’s innovative
high speed DDS core accepts a 32-bit frequency tuning word,
which results in an output tuning resolution of approximately
0.04 Hz with a 180 MHz system clock. The AD9851 contains
a unique 6 REFCLK Multiplier circuit that eliminates the
need for a high speed reference oscillator. The 6 REFCLK
Multiplier has minimal impact on SFDR and phase noise char-
acteristics. The AD9851 provides five bits of programmable
phase modulation resolution to enable phase shifting of its
output in increments of 11.25°.
The AD9851 contains an internal high speed comparator that
can be configured to accept the (externally) filtered output of the
DAC to generate a low jitter output pulse.
The frequency tuning, control, and phase modulation words are
asynchronously loaded into the AD9851 via a parallel or serial
loading format. The parallel load format consists of five iterative
loads of an 8-bit control word (byte). The first 8-bit byte controls
output phase, 6 REFCLK Multiplier, power-down enable and
loading format; the remaining bytes comprise the 32-bit frequency
tuning word. Serial loading is accomplished via a 40-bit serial data
stream entering through one of the parallel input bus lines. The
AD9851 uses advanced CMOS technology to provide this break-
through level of functionality on just 555 mW of power dissipation
(5 V supply), at the maximum clock rate of 180 MHz.
The AD9851 is available in a space-saving 28-lead SSOP,
surface-mount package that is pin-for-pin compatible with the
popular AD9850 125 MHz DDS. It is specified to operate over
the extended industrial temperature range of –40°C to +85°C
at >3.0 V supply voltage. Below 3.0 V, the specifications apply
over the commercial temperature range of 0°C to 85°C.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or oth-
erwise under any patent or patent rights of Analog Devices.Trademarks
and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2004 Analog Devices, Inc. All rights reserved.
1 page  
AD9851
Parameter
Temp
Test
Level
AD9851BRS
Min Typ Max
Unit
TIMING CHARACTERISTICS4
tWH, tWL (W_CLK Min Pulse Width High/Low)
tDS, tDH (Data to W_CLK Setup and Hold Times)
tFH, tFL (FQ_UD Min Pulse Width High/Low)
tCD (REFCLK Delay After FQ_UD)5
tFD (FQ_UD Min Delay After W_CLK)
tCF (Output Latency from FQ_UD)
Frequency Change
Phase Change
tRH (CLKIN Delay After RESET Rising Edge)
tRL (RESET Falling Edge After CLKIN)
tRR (Recovery from RESET)
tRS (Minimum RESET Width)
tOL (RESET Output Latency)
Wake-Up Time from Power-Down Mode6
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
V
3.5
3.5
7
3.5
7
18
13
3.5
3.5
2
5
13
5
ns
ns
ns
ns
ns
SYSCLK
Cycles
SYSCLK
Cycles
ns
ns
SYSCLK
Cycles
SYSCLK
Cycles
SYSCLK
Cycles
µs
CMOS LOGIC INPUTS
Logic 1 Voltage, 5 V Supply
Logic 1 Voltage, 3.3 V Supply
Logic 1 Voltage, 2.7 V Supply
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Rise/Fall Time
Input Capacitance
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
I
IV
IV
IV
I
I
IV
V
3.5 V
2.4 V
2.0 V
0.8 V
12 µA
12 µA
100 ns
3 pF
POWER SUPPLY
VS6 Current @:
62.5 MHz Clock, 2.7 V Supply
100 MHz Clock, 2.7 V Supply
62.5 MHz Clock, 3.3 V Supply
125 MHz Clock, 3.3 V Supply
62.5 MHz Clock, 5 V Supply
125 MHz Clock, 5 V Supply
180 MHz Clock, 5 V Supply
Power Dissipation @ :
62.5 MHz Clock, 5 V Supply
62.5 MHz Clock, 3.3 V Supply
62.5 MHz Clock, 2.7 V Supply
100 MHz Clock, 2.7 V Supply
125 MHz Clock, 5 V Supply
125 MHz Clock, 3.3 V Supply
180 MHz Clock, 5 V Supply
PDISS Power-Down Mode @:
5 V Supply
2.7 V Supply
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
30 35
40 50
35 45
55 70
50 65
70 90
110 130
250 325
115 150
85 95
110 135
365 450
180 230
555 650
17 55
4 20
mA
mA
mA
mA
mA
mA
mA
mW
mW
mW
mW
mW
mW
mW
mW
mW
NOTES
1+VS collectively refers to the positive voltages applied to DVDD, PVCC, and AVDD. Voltages applied to these pins should be of the same potential.
2Indicates the minimum signal levels required to reliably clock the device at the indicated supply voltages. This specifies the p-p signal level and dc offset needed when the
clocking signal is not of CMOS/TTL origin, i.e., a sine wave with 0 V dc offset.
3The comparator’s jitter contribution to any input signal. This is the minimum jitter on the outputs that can be expected from an ideal input. Considerably more output
jitter is seen when nonideal input signals are presented to the comparator inputs. Nonideal characteristics include the presence of extraneous, nonharmonic signals (spur’s,
noise), slower slew rate, and low comparator overdrive.
4Timing of input signals FQ_UD, WCLK, RESET are asynchronous to the reference clock; however, the presence of a reference clock is required to implement those
functions. In the absence of a reference clock, the AD9851 automatically enters power-down mode rendering the IC, including the comparator, inoperable until a refer-
ence clock is restored. Very high speed updates of frequency/phase word will require FQ_UD and WCLK to be externally synchronized with the external reference clock to
ensure proper timing.
5Not applicable when 6 REFCLK Multiplier is engaged.
6Assumes no capacitive load on DACBP (Pin 17).
Specifications subject to change without notice.
REV. D
–3–
5 Page 
70
1.1MHz
65
60
40.1MHz
55
50
70.1MHz
45
40
5
10 15
MAXIMUM DAC IOUT – mA
20
TPC 17. Effect of DAC maximum output current on
wideband (0 to 72 MHz) SFDR at three representa-
tive DAC output frequencies: 1.1 MHz, 40.1 MHz,
and 70.1 MHz. VS = 5 V, 180 MHz system clock (6
REFCLK multiplier disabled). Currents are set using
appropriate values of RSET.
AD9851
600
500
400 VS = +3.3V
300
VS = +5V
200
100
0
0 20 40 60 80 100 120 140 160
INPUT FREQUENCY – MHz
TPC 18. Minimum p-p input signal needed to tog-
gle the AD9851 comparator output. Comparator
input is a sine wave compared with a fixed volt-
age threshold. Use this data in addition to sin(x)/x
rolloff and any filter losses to determine whether
adequate signal is being presented to the AD9851
comparator.
REV. D
–9–
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet AD9851.PDF ] | |
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