|
|
PDF AD9850 Data sheet ( Hoja de datos )
| Número de pieza | AD9850 | |
| Descripción | 125 MHz Complete DDS Synthesizer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD9850 (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
|
No Preview Available !
a
FEATURES
125 MHz Clock Rate
On-Chip High Performance DAC and High Speed
Comparator
DAC SFDR > 50 dB @ 40 MHz AOUT
32-Bit Frequency Tuning Word
Simplified Control Interface: Parallel Byte or Serial
Loading Format
Phase Modulation Capability
3.3 V or 5 V Single-Supply Operation
Low Power: 380 mW @ 125 MHz (5 V)
Low Power: 155 mW @ 110 MHz (3.3 V)
Power-Down Function
Ultrasmall 28-Lead SSOP Packaging
APPLICATIONS
Frequency/Phase—Agile Sine Wave Synthesis
Clock Recovery and Locking Circuitry for Digital
Communications
Digitally Controlled ADC Encode Generator
Agile Local Oscillator Applications
CMOS, 125 MHz
Complete DDS Synthesizer
AD9850
FUNCTIONAL BLOCK DIAGRAM
+VS GND
REF
CLOCK IN
MASTER
RESET
FREQUENCY
UPDATE/
DATA REGISTER
RESET
WORD LOAD
CLOCK
HIGH SPEED
DDS
32-BIT
TUNING
WORD
PHASE
AND
CONTROL
WORDS
FREQUENCY/PHASE
DATA REGISTER
DATA INPUT REGISTER
SERIAL
LOAD
PARALLEL
LOAD
10-BIT
DAC
DAC RSET
ANALOG
OUT
ANALOG
IN
COMPARATOR
CLOCK OUT
CLOCK OUT
AD9850
1-BIT
8-BITS
40 LOADS 5 LOADS
FREQUENCY, PHASE, AND CONTROL
DATA INPUT
GENERAL DESCRIPTION
The AD9850 is a highly integrated device that uses advanced
DDS technology coupled with an internal high speed, high
performance D/A converter and comparator to form a com-
plete, digitally programmable frequency synthesizer and
clock generator function. When referenced to an accurate
clock source, the AD9850 generates a spectrally pure, fre-
quency/phase programmable, analog output sine wave. This
sine wave can be used directly as a frequency source, or it can
be converted to a square wave for agile-clock generator applica-
tions. The AD9850’s innovative high speed DDS core provides
a 32-bit frequency tuning word, which results in an output
tuning resolution of 0.0291 Hz for a 125 MHz reference clock
input. The AD9850’s circuit architecture allows the generation
of output frequencies of up to one-half the reference clock
frequency (or 62.5 MHz), and the output frequency can be digi-
tally changed (asynchronously) at a rate of up to 23 million new
frequencies per second. The device also provides five bits of
digitally controlled phase modulation, which enables phase
shifting of its output in increments of 180°, 90°, 45°, 22.5°,
11.25°, and any combination thereof. The AD9850 also contains
a high speed comparator that can be configured to accept the
(externally) filtered output of the DAC to generate a low jitter
square wave output. This facilitates the device’s use as an
agile clock generator function.
The frequency tuning, control, and phase modulation words are
loaded into the AD9850 via a parallel byte or serial loading
format. The parallel load format consists of five iterative loads
of an 8-bit control word (byte). The first byte controls phase
modulation, power-down enable, and loading format; Bytes 2 to
5 comprise the 32-bit frequency tuning word. Serial loading is
accomplished via a 40-bit serial data stream on a single pin. The
AD9850 Complete DDS uses advanced CMOS technology to
provide this breakthrough level of functionality and performance
on just 155 mW of power dissipation (3.3 V supply).
The AD9850 is available in a space-saving 28-lead SSOP,
surface-mount package. It is specified to operate over the
extended industrial temperature range of –40°C to +85°C.
REV. H
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
Parameter
CMOS LOGIC INPUTS (Including CLKIN)
Logic 1 Voltage, 5 V Supply
Logic 1 Voltage, 3.3 V Supply
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
POWER SUPPLY (AOUT = 1/3 CLKIN)
+VS Current @
62.5 MHz Clock, 3.3 V Supply
110 MHz Clock, 3.3 V Supply
62.5 MHz Clock, 5 V Supply
125 MHz Clock, 5 V Supply
PDISS @
62.5 MHz Clock, 3.3 V Supply
110 MHz Clock, 3.3 V Supply
62.5 MHz Clock, 5 V Supply
125 MHz Clock, 5 V Supply
PDISS Power-Down Mode
5 V Supply
3.3 V Supply
*Tested by measuring output duty cycle variation.
Specifications subject to change without notice.
Temp
25°C
25°C
25°C
25°C
25°C
25°C
Test Level
I
IV
IV
I
I
V
AD9850
AD9850BRS
Min Typ Max Unit
3.5
2.4
3
V
V
0.8 V
12 µA
12 µA
pF
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full V
Full V
30 48 mA
47 60 mA
44 64 mA
76 96 mA
100 160 mW
155 200 mW
220 320 mW
380 480 mW
30 mW
10 mW
TIMING CHARACTERISTICS*(VS = 5 V ؎ 5% except as noted, RSET = 3.9 k⍀)
Parameter
Temp
Test Level
AD9850BRS
Min Typ Max
tDS (Data Setup Time)
tDH (Data Hold Time)
tWH (W_CLK Minimum Pulse Width High)
tWL (W_CLK Minimum Pulse Width Low)
tWD (W_CLK Delay after FQ_UD)
tCD (CLKIN Delay after FQ_UD)
tFH (FQ_UD High)
tFL (FQ_UD Low)
tCF (Output Latency from FQ_UD)
Frequency Change
Phase Change
tFD (FQ_UD Minimum Delay after W_CLK)
tRH (CLKIN Delay after RESET Rising Edge)
tRL (RESET Falling Edge after CLKIN)
tRS (Minimum RESET Width)
tOL (RESET Output Latency)
tRR (Recovery from RESET)
Wake-Up Time from Power-Down Mode
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
V
3.5
3.5
3.5
3.5
7.0
3.5
7.0
7.0
18
13
7.0
3.5
3.5
5
13
2
5
*Control functions are asynchronous with CLKIN.
Specifications subject to change without notice.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
CLKIN Cycles
CLKIN Cycles
ns
ns
ns
CLKIN Cycles
CLKIN Cycles
CLKIN Cycles
µs
REV. H
–3–
5 Page 
AD9850
REF
CLOCK
DDS CIRCUITRY
N
PHASE
ACCUMULATOR
AMPLITUDE/COS
CONV.
ALGORITHM
D/A
CONVERTER
LP COMPARATOR
CLK
OUT
TUNING WORD SPECIFIES
OUTPUT FREQUENCY
AS A FRACTION OF REF
CLOCK FREQUENCY
IN DIGITAL DOMAIN
COS (x)
Figure 4. Basic DDS Block Diagram and Signal Flow of AD9850
AD9850 is a sampled signal, its output spectrum follows the
Nyquist sampling theorem. Specifically, its output spectrum
contains the fundamental plus aliased signals (images) that
occur at multiples of the reference clock frequency ± the
selected output frequency. A graphical representation of the
sampled spectrum, with aliased images, is shown in Figure 5.
fOUT
sin(x)/x ENVELOPE x=()fo/fc
fc – fo
fc + fo
fc
2fc – fo
2fc + fo
3fc – fo
20MHz
80MHz
120MHz
FUNDAMENTAL 1ST IMAGE 2ND IMAGE
100MHz
REFERENCE CLOCK
FREQUENCY
180MHz
3RD IMAGE
220MHz
4TH IMAGE
280MHz
5TH IMAGE
Figure 5. Output Spectrum of a Sampled Signal
In this example, the reference clock is 100 MHz and the output
frequency is set to 20 MHz. As can be seen, the aliased images
are very prominent and of a relatively high energy level as deter-
mined by the sin(x)/x roll-off of the quantized D/A converter
output. In fact, depending on the fo/reference clock relation-
ship, the first aliased image can be on the order of –3 dB below
the fundamental. A low-pass filter is generally placed between
the output of the D/A converter and the input of the com-
parator to further suppress the effects of aliased images. Obvi-
ously, consideration must be given to the relationship of the
selected output frequency and the reference clock frequency
to avoid unwanted (and unexpected) output anomalies.
To apply the AD9850 as a clock generator, limit the selected
output frequency to <33% of reference clock frequency, and
thereby avoid generating aliased signals that fall within, or close
to, the output band of interest (generally dc-selected output fre-
quency). This practice eases the complexity (and cost) of the
external filter requirement for the clock generator application.
The reference clock frequency of the AD9850 has a minimum
limitation of 1 MHz. The device has internal circuitry that
senses when the minimum clock rate threshold has been exceeded
and automatically places itself in the power-down mode. When
in this state, if the clock frequency again exceeds the threshold,
the device resumes normal operation. This shutdown mode
prevents excessive current leakage in the dynamic registers of
the device.
The D/A converter output and comparator inputs are available
as differential signals that can be flexibly configured in any
manner desired to achieve the objectives of the end system. The
typical application of the AD9850 is with single-ended output/
input analog signals, a single low-pass filter, and the generation
of the comparator reference midpoint from the differential DAC
output as shown in Figure 1.
Programming the AD9850
The AD9850 contains a 40-bit register that is used to program the
32-bit frequency control word, the 5-bit phase modulation word,
and the power-down function. This register can be loaded in a
parallel or serial mode.
In the parallel load mode, the register is loaded via an 8-bit bus;
the full 40-bit word requires five iterations of the 8-bit word.
The W_CLK and FQ_UD signals are used to address and load
the registers. The rising edge of FQ_UD loads the (up to) 40-bit
control data-word into the device and resets the address pointer
to the first register. Subsequent W_CLK rising edges load the
8-bit data on words [7:0] and move the pointer to the next
register. After five loads, W_CLK edges are ignored until either
a reset or an FQ_UD rising edge resets the address pointer to
the first register.
In serial load mode, subsequent rising edges of W_CLK shift
the 1-bit data on Pin 25 (D7) through the 40 bits of program-
ming information. After 40 bits are shifted through, an FQ_UD
pulse is required to update the output frequency (or phase).
The function assignments of the data and control words are
shown in Table III; the detailed timing sequence for updating
the output frequency and/or phase, resetting the device, and
powering up/down, are shown in the timing diagrams of
Figures 6 through 12.
Note: There are specific control codes, used for factory test
purposes, that render the AD9850 temporarily inoperable. The
user must take deliberate precaution to avoid inputting the
codes listed in Table II.
REV. H
–9–
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet AD9850.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD9850 | 125 MHz Complete DDS Synthesizer | Analog Devices |
| AD9851 | CMOS 180 MHz DDS/DAC Synthesizer | Analog Devices |
| AD9852 | CMOS 300 MHz Complete-DDS | Analog Devices |
| AD9853 | Programmable Digital OPSK/16-QAM Modulator | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |