PDF AD9843A Data sheet ( Hoja de datos )

Número de pieza	AD9843A
Descripción	Complete 10-Bit 20 MSPS CCD Signal Processor
Fabricantes	Analog Devices
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No Preview Available ! a FEATURES 20 MSPS Correlated Double Sampler (CDS) 4 dB ؎ 6 dB Variable CDS Gain with 6-Bit Resolution 2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA) Low Noise Clamp Circuits Analog Preblanking Function 10-Bit 20 MSPS A/D Converter Auxiliary Inputs with VGA and Input Clamp 3-Wire Serial Digital Interface 3 V Single Supply Operation Low Power: 65 mW @ 2.7 V Supply 48-Lead LQFP Package APPLICATIONS Digital Still Cameras Digital Video Camcorders PC Cameras Complete 10-Bit 20 MSPS CCD Signal Processor AD9843A PRODUCT DESCRIPTION The AD9843A is a complete analog signal processor for CCD applications. It features a 20 MHz single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan area CCD arrays. The AD9843A’s signal chain consists of an input clamp, correlated double sampler (CDS), digitally controlled variable gain amplifier (VGA), black level clamp, and 10-bit A/D converter. Additional input modes are provided for processing analog video signals. The internal registers are programmed through a 3-wire serial digital interface. Programmable features include gain adjust- ment, black level adjustment, input configuration, and power- down modes. The AD9843A operates from a single 3 V power supply, typi- cally dissipates 78 mW, and is packaged in a 48-lead LQFP. CCDIN CLPDM AUX1IN AUX2IN PBLK FUNCTIONAL BLOCK DIAGRAM AVDD AVSS CLPOB 4dB؎6dB CDS CLP 2:1 MUX BUF CLP AD9843A 2:1 MUX 2dB~36dB VGA CLP 10-BIT ADC 10 10 6 INTERNAL REGISTERS OFFSET DAC 8 BANDGAP REFERENCE INTERNAL BIAS DIGITAL INTERFACE INTERNAL TIMING DRVDD DRVSS DOUT VRT VRB CML DVDD DVSS SL SCK SDATA SHP SHD DATACLK REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 1 page AD9843A TIMING SPECIFICATIONS (CL = 20 pF, fSAMP = 20 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7. Serial Timing in Figures 8–10.) Parameter Symbol Min Typ Max Unit SAMPLE CLOCKS DATACLK, SHP, SHD Clock Period DATACLK High/Low Pulsewidth SHP Pulsewidth SHD Pulsewidth CLPDM Pulsewidth CLPOB Pulsewidth1 SHP Rising Edge to SHD Falling Edge SHP Rising Edge to SHD Rising Edge Internal Clock Delay Inhibited Clock Period DATA OUTPUTS Output Delay Output Hold Time Pipeline Delay tCONV tADC tSHP tSHD tCDM tCOB tS1 tS2 tID tINH tOD tH 48 20 7 7 4 2 0 20 10 7.0 50 25 12.5 12.5 10 20 12.5 25 3.0 14.5 16 7.6 9 ns ns ns ns Pixels Pixels ns ns ns ns ns ns Cycles SERIAL INTERFACE Maximum SCK Frequency SL to SCK Setup Time SCK to SL Hold Time SDATA Valid to SCK Rising Edge Setup SCK Falling Edge to SDATA Valid Hold SCK Falling Edge to SDATA Valid Read fSCLK tLS tLH tDS tDH tDV 10 10 10 10 10 10 NOTES 1Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance. Specifications subject to change without notice. MHz ns ns ns ns ns ABSOLUTE MAXIMUM RATINGS Parameter With Respect To Min Max Unit AVDD1, AVDD2 DVDD1, DVDD2 DRVDD Digital Outputs SHP, SHD, DATACLK CLPOB, CLPDM, PBLK SCK, SL, SDATA VRT, VRB, CMLEVEL BYP1-4, CCDIN Junction Temperature Lead Temperature (10 sec) AVSS DVSS DRVSS DRVSS DVSS DVSS DVSS AVSS AVSS –0.3 +3.9 V –0.3 +3.9 V –0.3 +3.9 V –0.3 DRVDD + 0.3 V –0.3 DVDD + 0.3 V –0.3 DVDD + 0.3 V –0.3 DVDD + 0.3 V –0.3 AVDD + 0.3 V –0.3 AVDD + 0.3 V 150 °C 300 °C ORDERING GUIDE Model Temperature Range AD9843AJST –20°C to +85°C Package Description Thin Plastic Quad Flatpack (LQFP) Package Option ST-48 THERMAL CHARACTERISTICS Thermal Resistance 48-Lead LQFP Package θJA = 92°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9843A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 –5– 5 Page AD9843A Table II. Operation Register Contents (Default Value x000) Optical Black Clamp Reset D10 D9 D8 D7 D6 D5 D4 Power-Down Modes D3 D2 Channel Selection D1 D0 0* 0* 0* 1** 0* 0 Enable Clamping 0 Normal 0 0 Normal Power 0 0 CCD-Mode 1 Disable Clamping 1 Reset All 0 1 Fast Recovery 0 1 AUX1-Mode Registers 1 0 Standby 1 0 AUX2-Mode to Default 1 1 Total Power-Down 1 1 Test Only Must be set to zero. Set to one. Table III. VGA Gain Register Contents (Default Value x096) MSB D10 D9 D8 X0 0 11 11 LSB D7 D6 D5 D4 D3 D2 D1 D0 Gain (dB) 0 1 0 1 1 1 1 1 2.0 •• •• •• 1 1 1 1 1 1 1 0 35.965 1 1 1 1 1 1 1 1 36.0 Table IV. Clamp Level Register Contents (Default Value x080) MSB LSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XX X 0 0 0 0 00 0 0 0000 00 0 1 0000 00 1 0 • • • 11111110 11111111 Clamp Level (LSB) 0 0.25 0.5 • • • 63.5 63.75 Table V. Control Register Contents (Default Value x000) Data Out D10 D9 D8 D7 DATACLK D6 CLP/PBLK D5 SHP/SHD D4 CDS Gain D3 D2 D1 D0 X 0 Enable 0 0* 0 Rising Edge Trigger 0 Active Low 0 Active Low 0 Disabled** 0* 0* 0* 1 Three-State 1 Falling Edge Trigger 1 Active High 1 Active High 1 Enabled Must be set to zero. When D3 = 0 (CDS Gain Disabled), the CDS Gain Register is fixed at 4 dB (Code 63 dec). Table VI. CDS Gain Register Contents (Default Value x000) D10 D9 D8 MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 Gain (dB) XX X XX0 0 0 0 0 0 +4.3 •• •• •• 0 1 1 1 1 0 +10.0 1 0 0 0 0 0 –2.0 •• •• •• 1 1 1 1 1 1 +4.0 *Control Register Bit D3 must be set high for the CDS Gain Register to be used. REV. 0 –11– 11 Page

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