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PDF AD9833 Data sheet ( Hoja de datos )
| Número de pieza | AD9833 | |
| Descripción | Programmable Waveform Generator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
FEATURES
Digitally programmable frequency and phase
12.65 mW power consumption at 3 V
0 MHz to 12.5 MHz output frequency range
28-bit resolution: 0.1 Hz at 25 MHz reference clock
Sinusoidal, triangular, and square wave outputs
2.3 V to 5.5 V power supply
No external components required
3-wire SPI interface
Extended temperature range: −40°C to +105°C
Power-down option
10-lead MSOP package
Qualified for automotive applications
APPLICATIONS
Frequency stimulus/waveform generation
Liquid and gas flow measurement
Sensory applications: proximity, motion,
and defect detection
Line loss/attenuation
Test and medical equipment
Sweep/clock generators
Time domain reflectometry (TDR) applications
Low Power, 12.65 mW, 2.3 V to 5.5 V,
Programmable Waveform Generator
AD9833
GENERAL DESCRIPTION
The AD9833 is a low power, programmable waveform generator
capable of producing sine, triangular, and square wave outputs.
Waveform generation is required in various types of sensing,
actuation, and time domain reflectometry (TDR) applications.
The output frequency and phase are software programmable,
allowing easy tuning. No external components are needed. The
frequency registers are 28 bits wide: with a 25 MHz clock rate,
resolution of 0.1 Hz can be achieved; with a 1 MHz clock rate,
the AD9833 can be tuned to 0.004 Hz resolution.
The AD9833 is written to via a 3-wire serial interface. This serial
interface operates at clock rates up to 40 MHz and is compatible
with DSP and microcontroller standards. The device operates
with a power supply from 2.3 V to 5.5 V.
The AD9833 has a power-down function (SLEEP). This function
allows sections of the device that are not being used to be powered
down, thus minimizing the current consumption of the part. For
example, the DAC can be powered down when a clock output is
being generated.
The AD9833 is available in a 10-lead MSOP package.
AGND DGND
FUNCTIONAL BLOCK DIAGRAM
VDD
CAP/2.5V
MCLK
AVDD/
DVDD
REGULATOR
2.5V
ON-BOARD
REFERENCE
FULL-SCALE
CONTROL
FREQ0 REG
FREQ1 REG
MUX
PHASE
ACCUMUL ATOR
(28-BIT)
PHASE0 REG
PHASE1 REG
MUX
CONTROL REGISTER
SERIAL INTERFACE
AND
CONTROL LOGIC
12
SIN
MUX
10-BIT DAC
ROM
MSB
DIVIDE
BY 2
MUX
AD9833
R
200Ω
COMP
VOUT
FSYNC SCLK SDATA
Figure 1.
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD9833
SPECIFICATIONS
VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, RSET = 6.8 kΩ for VOUT, unless otherwise noted.
Table 1.
Parameter1
Min Typ Max Unit Test Conditions/Comments
SIGNAL DAC SPECIFICATIONS
Resolution
10 Bits
Update Rate
25 MSPS
VOUT Maximum
0.65 V
VOUT Minimum
38 mV
VOUT Temperature Coefficient
200 ppm/°C
DC Accuracy
Integral Nonlinearity
±1.0 LSB
Differential Nonlinearity
±0.5 LSB
DDS SPECIFICATIONS (SFDR)
Dynamic Specifications
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
55
60 dB fMCLK = 25 MHz, fOUT = fMCLK/4096
−66 −56 dBc fMCLK = 25 MHz, fOUT = fMCLK/4096
Wideband (0 to Nyquist)
Narrow-Band (±200 kHz)
Clock Feedthrough
−60 dBc fMCLK = 25 MHz, fOUT = fMCLK/50
−78 dBc fMCLK = 25 MHz, fOUT = fMCLK/50
−60 dBc
Wake-Up Time
1 ms
LOGIC INPUTS
Input High Voltage, VINH
1.7
2.0
V 2.3 V to 2.7 V power supply
V 2.7 V to 3.6 V power supply
2.8 V 4.5 V to 5.5 V power supply
Input Low Voltage, VINL
0.5 V
0.7 V
2.3 V to 2.7 V power supply
2.7 V to 3.6 V power supply
0.8 V
4.5 V to 5.5 V power supply
Input Current, IINH/IINL
Input Capacitance, CIN
POWER SUPPLIES
VDD
3
2.3
10 µA
pF
5.5 V
fMCLK = 25 MHz, fOUT = fMCLK/4096
IDD
Low Power Sleep Mode
4.5 5.5 mA IDD code dependent; see Figure 7
0.5 mA DAC powered down, MCLK running
1 Operating temperature range is −40°C to +105°C; typical specifications are at 25°C.
100nF
CAP/2.5V
REGULATOR
AD9833
12 SIN
ROM
10nF
VDD
COMP
VOUT
10-BIT DAC
20pF
Figure 2. Test Circuit Used to Test Specifications
Rev. E | Page 3 of 24
5 Page 
Data Sheet
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
RWB 300
VWB 100
FREQUENCY (Hz)
1M
ST 100 SEC
Figure 18. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 60 kHz,
Frequency Word = 0x009D495
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
RWB 1k
VWB 300
FREQUENCY (Hz)
12.5M
ST 100 SEC
Figure 19. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 600 kHz,
Frequency Word = 0x0624DD3
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
RWB 1k
VWB 300
FREQUENCY (Hz)
12.5M
ST 100 SEC
Figure 20. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 2.4 MHz,
Frequency Word = 0x189374D
AD9833
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
RWB 1k
VWB 300
FREQUENCY (Hz)
12.5M
ST 100 SEC
Figure 21. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 3.857 MHz = fMCLK/7,
Frequency Word = 0x2492492
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
RWB 1k
VWB 300
FREQUENCY (Hz)
12.5M
ST 100 SEC
Figure 22. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 8.333 MHz = fMCLK/3,
Frequency Word = 0x5555555
Rev. E | Page 9 of 24
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet AD9833.PDF ] | |
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