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PDF AD9774 Data sheet ( Hoja de datos )
| Número de pieza | AD9774 | |
| Descripción | 14-Bit/ 32 MSPS TxDAC with 4x Interpolation Filters | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
14-Bit, 32 MSPS TxDAC+™
with 4؋ Interpolation Filters
AD9774
FEATURES
Single 3 V or 5 V Supply
14-Bit DAC Resolution and Input Data Width
32 MSPS Input Data Rate at 5 V
13.5 MHz Reconstruction Bandwidth
12 ENOBS @ 1 MHz
77 dBc SFDR @ 5 MHz
4؋ Interpolation Filter
69 dB Image Rejection
84% Passband to Nyquist Ratio
0.002 dB Passband Ripple
23 3/4 Cycle Latency
Internal 4؋ Clock Multiplier
On-Chip 1.20 V Reference
44-Lead MQFP Package
APPLICATIONS
Communication Transmit Channel:
Wireless Basestations
ADSL/HFC Modems
Direct Digital Synthesis (DDS)
PRODUCT DESCRIPTION
The AD9774 is a single supply, oversampling, 14-bit digital-to-
analog converter (DAC) optimized for waveform reconstruction
applications requiring exceptional dynamic range. Manufac-
tured on an advanced CMOS process, it integrates a complete,
low distortion 14-bit DAC with a 4× digital interpolation filter
and clock multiplier. The two-stage, 4× digital interpolation
filter provides more than a six-fold reduction in the complexity
of the analog reconstruction-filter. It does so by multiplying the
input data rate by a factor of four while simultaneously suppressing
the original inband images by more than 69 dB. The on-chip
clock multiplier provides all the necessary clocks. The AD9774
can reconstruct full-scale waveforms having bandwidths as high
as 13.5 MHz when operating at an input data rate of 32 MSPS
and a DAC output rate of 128 MSPS.
The 14-bit DAC provides differential current outputs to support
differential or single-ended applications. A segmented current
source architecture is combined with a proprietary switching tech-
nique to reduce spurious components and enhance dynamic per-
formance. Matching between the two current outputs ensures
enhanced dynamic performance in a differential output configura-
tion. The differential current outputs may be fed into a transformer
or tied directly to an output resistor to provide two complementary,
single-ended voltage outputs. A differential op amp topology can
also be used to obtain a single-ended output voltage. The output
voltage compliance range is nominally 1.25 V.
TxDAC+ is a trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
PLL VCO PLL
CLK4؋IN PLLLOCK ENABLE IN/EXT DIVIDE
CLK IN/OUT
DATA
INPUTS
(DB13-DB0)
AD9774
PLL CLOCK
MULTIPLIER
1؋ 2؋ 4؋
14 EDGE 14
TRIGGERED
2؋
LATCHES
14
2؋
4؋
14
14-BIT
DAC
PLLCOM
LPF
PLLVDD
IOUTA
IOUTB
SNOOZE
SLEEP
+1.2V REFERENCE
AND CONTROL AMP
REFIO
FSADJ
DCOM DVDD ICOMP ACOM AVDD REFLO REFCOMP
Edge-triggered input latches, a 4× clock multiplier, and a tem-
perature compensated bandgap reference have also been inte-
grated to provide a complete monolithic DAC solution. Flexible
supply options support +3 V and +5 V CMOS logic families.
TTL logic levels can also be accommodated by reducing the
AD9774 digital supply.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9774 can be driven
by the on-chip reference or by a variety of external reference
voltages. The full-scale current of the AD9774 can be adjusted
over a 2 mA to 20 mA range, thus providing additional gain
ranging capabilities.
The AD9774 is available in a 44-lead MQFP package. It is
specified for operation over the industrial temperature range.
PRODUCT HIGHLIGHTS
1. On-Chip 4× interpolation filter eases analog reconstruction
filter requirements by suppressing the first three images by 69 dB.
2. Low glitch and fast settling time provide outstanding dynamic
performance for waveform reconstruction or digital synthesis
requirements, including communications.
3. On-chip, edge-triggered input CMOS latches interface readily
to CMOS and TTL logic families. The AD9774 can support
input data rates up to 32 MSPS.
4. A temperature compensated, 1.20 V bandgap reference is
included on-chip, providing a complete DAC solution. An
external reference may also be used.
5. The current output(s) of the AD9774 can easily be configured
for various single-ended or differential circuit topologies.
6. On-chip clock multiplier generates all the high-speed clocks
required by the internal interpolation filters. Both 2× and 4×
clocks are generated from the lower rate data clock supplied
by the user.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
1 page  
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
0
0.5 1.0 1.5
FREQUENCY – DC TO 2؋ fCLOCK
2.0
Figure 2a. FIR Filter Frequency Response
1.0
0.8
0.6
0.4
0.2
0.0
–0.2
–0.4
0 10 20 30 40 50 60 70 80
TIME – Samples
Figure 2b. FIR Filter Impulse Response
AD9774
Table I. Integer Filter Coefficients for First Stage Interpola-
tion Filter (55-Tap Halfband FIR Filter)
Lower
Coefficient
H(1)
H(2)
H(3)
H(4)
H(5)
H(6)
H(7)
H(8)
H(9)
H(10)
H(11)
H(12)
H(13)
H(14)
H(15)
H(16)
H(17)
H(18)
H(19)
H(20)
H(21)
H(22)
H(23)
H(24)
H(25)
H(26)
H(27)
H(28)
Upper
Coefficient
H(55)
H(54)
H(53)
H(52)
H(51)
H(50)
H(49)
H(48)
H(47)
H(46)
H(45)
H(44)
H(43)
H(42)
H(41)
H(40)
H(39)
H(38)
H(37)
H(36)
H(35)
H(34)
H(33)
H(32)
H(31)
H(30)
H(29)
Integer
Value
–1
0
3
0
–7
0
15
0
–28
0
49
0
–81
0
128
0
–196
0
295
0
–447
0
706
0
–1274
0
3976
6276
Table II. Integer Filter Coefficients for Second Stage Inter-
polation Filter (23-Tap Halfband FIR Filter)
Lower
Coefficient
H(1)
H(2)
H(3)
H(4)
H(5)
H(6)
H(7)
H(8)
H(9)
H(10)
H(11)
H(12)
Upper
Coefficient
H(23)
H(22)
H(21)
H(20)
H(19)
H(18)
H(17)
H(16)
H(15)
H(14)
H(13)
Integer
Value
–6
0
37
0
–125
0
316
0
–736
0
2562
4096
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9774 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. B
–5–
WARNING!
ESD SENSITIVE DEVICE
5 Page 
AD9774
PLL CLOCK MULTIPLIER OPERATION
The Phase Lock Loop (PLL) Clock Multiplier is intrinsic to the
operation of the AD9774 in that it produces the necessary inter-
nally synchronized 1×, 2× and 4× clocks for the edge triggered
latches, interpolation filters and DACs. Figure 24 shows a func-
tional block diagram of the PLL Clock Multiplier, which con-
sists of a phase detector, a charge pump, a voltage controlled
oscillator (VCO), a divide-by-N circuit and some control inputs/
outputs. It produces the required internal clocks for the AD9774
by using one of two possible externally applied reference clock
sources applied to either CLKIN or CLK4×IN. PLLENABLE
and VCO IN/EXT are active HIGH control inputs used to
enable the charge pump and VCO respectively.
To maintain optimum noise and distortion performance,
PLLVDD and DVDD should be set to similar voltage levels. If
a separate supply cannot be provided for PLLVDD, PLLVDD
can be tied to DVDD using an LC filter network similar to that
shown in Figure 41.
Many applications will select a reference clock operating at the
data input rate as shown in Figure 24. In this case, the external
clock source is applied to CLKIN and the PLL Clock Multiplier
is fully enabled by tying PLLENABLE and VCO IN/EXT to
PLLVDD. Note, CLKIN must adhere to the timing require-
ments shown in Figure 1. A 1.5 kΩ resistor and 0.01 µF ceramic
capacitor connected in series from LPF to PLLVDD are re-
quired to optimize the phase noise vs. settling/acquisition time
characteristics of the PLL. PLLLOCK is a control output, ac-
tive HIGH, which may be monitored upon system power-up to
indicate that the PLL is successfully “locked” to CLKIN. Note,
applications employing multiple AD9774 devices will benefit
from the PLL Clock Multiplier’s ability to ensure precise simul-
taneous updating/phase synchronization of these devices when
driven by the same input clock source.
PLLDIVIDE is used to preset the “lock-in” range of the PLL. It
should be tied to PLLCOM if CLKIN is greater than 10 MHz
and to PLLVDD if CLKIN is between 5.5 MHz and 10 MHz.
For operation below 5.5 MHz (i.e., input data rates less than
5.5 MSPS), the internal charge pump and VCO should be
disabled by tying PLLENABLE and VCO IN/EXT LOW. In
this case, the user MUST supply a system clock operating at 4×
the input data rate as discussed below.
CONNECT TO
PLLCOM
CLK
IN/OUT
PLL
DIVIDE
CONNECT TO
PLLVDD
PLLLOCK
PLL
ENABLE
PHASE
DETECTOR
CHARGE
PUMP
،8
،4 DIVIDE-
،2 BY-N
،1
AD9774
VCO
VCO
LPF
1.5k⍀
PLL
VDD
0.01F
PLL
COM
+2.7 TO
+5.5 VD
CLK
DCOM DVDD 4؋IN
VCO
IN/EXT
+2.7 TO +5.5 VD
Figure 24. Clock Multiplier with PLL Enabled
There are two cases in which a user may consider or be required
to disable the internal PLL Clock Multiplier and supply the
AD9774 with an external 4× system clock. Applications already
containing a system clock operating at four (i.e., 4×) the input
data rate may consider using it as the master clock source. Ap-
plications with input data rates less than 5.5 MSPS must use a
master 4× clock.
In any of these cases, the clock source is applied to CLK4×IN
and the PLL is partially disabled by typing PLLENABLE and
VCO IN/EXT to PLLCOM as shown in Figure 25. LPF may
remain open since this portion of the PLL circuitry is disabled.
The divide-by-N circuit still remains enabled providing a 1× or
2× internal clock at CLOCK IN/OUT depending on the state of
PLLDIVIDE. Since the digital input data is latched into the
AD9774 on the rising edge of the 1× clock, PLLDIVIDE should
be tied to PLLCOM such that the 1× clock appears as an output
at CLOCK IN/OUT. The input data should be stable 5 ns (i.e.,
data set-up) before the rising edge of the 1× clock appearing at
CLOCK IN/OUT and remain stable for 1 ns after the rising
edge (i.e., data hold) to ensure proper latching. Note, the rising
edge of the 1× clock occurs approximately 9 ns to 15 ns relative
to the falling edge of the CLK4× input. If a data timing issue
exists between the AD9774 and its external driver device, the
CLK4× input can be inverted via an external gate to ensure
proper set-up and hold time.
PLL CLK
DIVIDE IN/OUT
PLLLOCK
PLL
ENABLE
PHASE
DETECTOR
CHARGE
PUMP
LPF
،8
،4 DIVIDE-
،2 BY-N
،1
AD9774
VCO
VCO
PLL
VDD
PLL
COM
+2.7 TO +5.5 VD
CLK
DCOM DVDD 4؋IN
VCO
IN/EXT
+2.7 TO +5.5 VD
Figure 25. Clock Divider with PLL Disabled
DAC OPERATION
The 14-bit DAC along with the 1.2 V reference and reference
control amplifier is shown in Figure 26. The DAC consists of a
large PMOS current source array capable of providing up to
20 mA of full-scale current, IOUTFS. The array is divided into 31
equal currents which make up the five most significant bits
(MSBs). The next four bits or middle bits consist of 15 equal
current sources whose values are 1/16th of an MSB current
source. The remaining LSBs are binary weighted fractions of the
middle-bits current sources. All of these current sources are
switched to one or the other of two output nodes (i.e., IOUTA
or IOUTB) via PMOS differential current switches. Implement-
ing the middle and lower bits with current sources, instead of an
R-2R ladder, enhances its dynamic performance for multitone
or low amplitude signals and helps maintain the DAC’s high
output impedance (i.e., > 100 kΩ).
REV. B
–11–
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD9774.PDF ] | |
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