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Allegro MicroSystems - DMOS FULL-BRIDGE PWM MOTOR DRIVER

Numéro de référence A3959SLB
Description DMOS FULL-BRIDGE PWM MOTOR DRIVER
Fabricant Allegro MicroSystems 
Logo Allegro MicroSystems 





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A3959SLB fiche technique
3959
DMOS FULL-BRIDGE PWM
MOTOR DRIVER
A3959SLB (SOIC)
CP 1
CP2 2
CP1 3
PHASE
θ
4
ROSC 5
GROUND 6
GROUND 7
LOGIC SUPPLY 8 VDD
ENABLE 99
PFD2 10
BLANK 11
PFD1 12
24 VREG
23 SLEEP
NC 22
NO
CONNECTION
21 OUTB
VBB 20 LOAD SUPPLY
19 GROUND
18 GROUND
17 SENSE
16 OUTA
NC
15
NO
CONNECTION
14 EXT MODE
÷10 13 REF
Dwg. PP-069-4
Note that the A3959SLB(SOIC), A3959SB (DIP),
and A3959SLP (TSSOP) do not share a common
terminal assignment.
ABSOLUTE MAXIMUM RATINGS
Designed for pulse-width modulated (PWM) current control of dc
motors, the A3959SB, A3959SLB, and A3959SLP are capable of
output currents to ±3 A and operating voltages to 50 V. Internal fixed
off-time PWM current-control timing circuitry can be adjusted via
control inputs to operate in slow, fast, and mixed current-decay modes.
PHASE and ENABLE input terminals are provided for use in
controlling the speed and direction of a dc motor with externally
applied PWM-control signals. Internal synchronous rectification
control circuitry is provided to reduce power dissipation during PWM
operation.
Internal circuit protection includes thermal shutdown with
hysteresis, undervoltage monitoring of supply and charge pump, and
crossover-current protection. Special power-up sequencing is not
required.
The A3959SB/SLB/SLP is a choice of three power packages, a
24-pin plastic DIP with a copper batwing tab (package suffix ‘B’), a
24-lead plastic SOIC with a copper batwing tab (package suffix ‘LB’),
and a thin (<1.2 mm) 28-lead plastic TSSOP with an exposed thermal
pad (suffix ‘LP’). In all cases, the power tab is at ground potential and
needs no electrical isolation. Each package is available in a lead-
free version (100% matte tin leadframe).
Load Supply Voltage, VBB ......................... 50 V
Output Current, IOUT (Repetitive) ........... ±3.0 A
(Peak, <3 µs) ................................... ±6.0 A
Logic Supply Voltage, VDD ....................... 7.0 V
Logic Input Voltage Range, VIN
(Continuous) ............ -0.3 V to VDD + 0.3 V
(tw <30 ns) ............... -1.0 V to VDD + 1.0 V
Sense Voltage, VS (Continuous) .............. 0.5 V
(tw <3 µs) ........................................... 2.5 V
Reference Voltage, VREF ............................ VDD
Package Power Dissipation (TA = 25°C), PD
A3959SB ........................................ 3.3 W*
A3959SLB ...................................... 2.5 W*
A3959SLP ...................................... 3.1 W*
Operating Temp. Range, TA .... -20°C to +85°C
Junction Temperature, TJ ..................... +150°C
Storage Temp. Range, TS ..... -55°C to +150°C
Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under any
set of conditions, do not exceed the specified
current rating or a junction temperature of 150°C.
FEATURES
s ±3 A, 50 V Output Rating
s Low rDS(on) Outputs (270 m, Typical)
s Mixed, Fast, and Slow Current-Decay Modes
s Synchronous Rectification for Low Power Dissipation
s Internal UVLO and Thermal-Shutdown Circuitry
s Crossover-Current Protection
s Internal Oscillator for Digital PWM Timing
Always order by complete part number:
Part Number
A3959SB
Package
24-pin batwing DIP
RθJA*
38°C/W
A3959SB-T 24-pin batwing DIP; Lead-free
38°C/W
A3959SLB
24-lead batwing SOIC
50°C/W
A3959SLB-T 24-lead batwing SOIC; Lead-free 50°C/W
A3959SLP
28-lead thin shrink SOIC
40°C/W
A3959SLP-T 28-lead thin shrink SOIC; Lead-free 40°C/W
RθJT
6°C/W
6°C/W
6°C/W
6°C/W
* Double-sided board, one square inch copper each side. See also, Layout, page 7.

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