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Aeroflex Circuit Technology - ACT5231 32-Bit Superscaler Microprocessor

Numéro de référence ACT-5231PC-150F22Q
Description ACT5231 32-Bit Superscaler Microprocessor
Fabricant Aeroflex Circuit Technology 
Logo Aeroflex Circuit Technology 





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ACT-5231PC-150F22Q fiche technique
ACT5231
32-Bit Superscaler Microprocessor
Features
s Full militarized QED RM5231 microprocessor
s High-performance floating point unit
s Pinout compatible with popular RM5230 with split power sup
plies (2.5V and 3.3V)
q 532 MFLOPS single-precision performance
q Single cycle repeat rate for common single precision opera-tions
and some double precision operations
s Dual Issue superscalar microprocessor - can issue one
q Two cycle repeat rate for double precision multiply and double
integer and one floating-point instruction per cycle
precision combined multiply-add operations
q 133, 150 and 200 MHz operating frequencies – Consult Factory for
q Single cycle repeat rate for single precision combined multiply-
latest speeds
add operation
q 325 Dhrystone2.1 MIPS
q SPECInt95 5.0, SPECfp95 5.25
s MIPS IV instruction set
q Floating point multiply-add instruction increases performance in
s System interface optimized for embedded applications
signal processing and graphics applications
q 32-bit system interface lowers total system cost
q Conditional moves to reduce branch frequency
q High performance write protocols maximize uncached write
q Index address modes (register + register)
bandwidth with 600 MB per second peak throughput
q Operates at processor clock divisors 2, 2.5, 3, 3.5,4, 4.5, 5, 6, 7, 8, 9
q IEEE 1149.1 JTAG boundary scan
s
Embedded application enhancements
q Specialized DSP integer Multiply-Accumulate instruction and 3
operand multiply instruction
s Integrated on-chip caches
q I and D cache locking by set
q 32KB instruction and 32KB data - 2 way set associative and per
q Optional dedicated exception vector for interrupts
set locking
q Virtually indexed, physically tagged
q Write-back and write-through on per page basis
q Pipeline restart on first double for data cache misses
s Fully static CMOS design with power down logic
q Standby reduced power mode with WAIT instruction
q 2.7 W typical power @ 200MHz
q 2.5V core with 3.3V IO’s
s Integrated memory management unit
q Fully associative joint TLB (shared by I and D translations)
q 48 dual entries map 96 pages
s 128-pin Power Quad-4 package (F22), Consult Factory for
package configuration
q Variable page size (4KB to 16MB in 4x increments)
Block Diagram
Preliminary
eroflex Circuit Technology – RISC TurboEngines For The Future © SCD5231 REV 1 12/22/98

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