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ACS8510 fiches techniques PDF

Semtech Corporation - Synchronous Equipment Timing Source for SONET or SDH Network Elements

Numéro de référence ACS8510
Description Synchronous Equipment Timing Source for SONET or SDH Network Elements
Fabricant Semtech Corporation 
Logo Semtech Corporation 





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ACS8510 fiche technique
ADVANCED COMMUNCIATIONS
ACS8510 SETS
Synchronous Equipment Timing Source
for SONET or SDH Network Elements
FINAL
Description
The ACS8510 is a highly integrated, single-chip
solution for the Synchronous Equipment Timing
Source (SETS) function in a SONET or SDH Net-
work Element. The device generates SONET or
SDH Equipment Clocks (SEC) and frame synchro-
nization clocks. The ACS8510 is fully compliant
with the required specifications and standards.
The device supports Free-Run, Locked and
Holdover modes. It also supports all three types
of reference clock source: recovered line clock,
PDH network, and node synchronization. The
ACS8510 generates independent SEC and BITS
clocks, an 8 kHz Frame Synchronization clock
and a 2 kHz Multi-Frame Synchronization clock.
Two ACS8510 devices can be used together in a
Master/Slave configuration mode allowing sys-
tem protection against a single ACS8510 failure.
A microprocessor port is incorporated, providing
access to the configuration and status registers
for device setup and monitoring. The ACS8510
supports IEEE 1149.1 JTAG boundary scan.
* Meets Holdover requirements, lowest bandwidth 0.1 Hz.
Block Diagram
Features
•Suitable for Stratum 3E*, 3, 4E and 4 SONET
or SDH Equipment Clock (SEC) applications
•Meets AT&T, ITU-T, ETSI and Telcordia specifi-
cations
•Accepts 14 individual input reference clocks
•Generates 11 output clocks
•Supports Free-Run, Locked and Holdover
modes of operation
•Robust input clock source quality monitoring on
all inputs
•Automatic “hit-less” source switchover on loss
of input
•Phase build-out for output clock phase conti-
nuity during input switchover and mode transi-
tions
•Microprocessor interface - Intel, Motorola,
Serial, Multiplexed, EEPROM
•Programmable wander and jitter tracking/
attenuation 0.1 Hz to 20 Hz
•Support for Master/Slave device configuration
alignment and hot/standby redundancy
•IEEE 1149.1 JTAG Boundary Scan
•Single 3.3 v operation. 5 v I/O compatible
•Operating temperature (ambient) -40°C to
+85°C
•Available in 100 pin LQFP package
14 Inp ut
Referenc e
Source
includin g:
AM I 64/8 kHz
2 kHz
8 kHz
N x 8 kHz
1.544 MHz
2.048 MHz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
Inp ut
Ports
6xTIN1
4xTIN2
4xTIN3
MFrSync
T CK
TDI IEEE
TMS 1149.1
T RST
TDO JTAG
TOUT4
se lec tor
Monitors
Div ider
Dig ital
PFD Loop
Filter
DPLL/F req. Synthesis
DTO
TO UT 0
se lec tor
Div ider
Dig ital
PFD Loop DTO
Filter
DPLL/Freq. S ynthesis
Chip C lock
Ge nera tor
P riorit y
T able
Re gis ter
Set
Micropro cessor
Port
TCXO (*OCXO)
CLK
Revision 2.07/Jan 2001 ã2001 Semtech Corp
A PLL
Frequency
Dividers
O utp ut
Ports
2xT O UT 4
7xT O UT 0
MFrSync
FrSync
11 Outp ut Ports
includin g:
1.544/2.048 M Hz
3.088/4.096 M Hz
6.176/8.182 M Hz
12.352/16.384 M Hz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
311.04 MHz
AM I 64/8 kHz
2 kHz MFrSy nc
8 kHz FrSy nc
www.semtech.com

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