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ACS174KMSR-03 fiches techniques PDF

Intersil Corporation - Radiation Hardened Hex D-Type Flip-Flop with Reset

Numéro de référence ACS174KMSR-03
Description Radiation Hardened Hex D-Type Flip-Flop with Reset
Fabricant Intersil Corporation 
Logo Intersil Corporation 





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ACS174KMSR-03 fiche technique
Data Sheet
ACS174MS
July 1999
File Number 4762
Radiation Hardened Hex D-Type Flip-Flop
with Reset
The Radiation Hardened ACS174MS is a Hex D-Type Flip-
Flop with Reset. Information at the D input is transferred to
the Q output on the positive-going transition of the clock. All
six flip-flops are controlled by a common clock (CP) and a
common reset (MR). Resetting is accomplished by a LOW
level independent of the clock. All inputs are buffered and
the outputs are designed for balanced propagation delay
and transition times.
The ACS174MS is fabricated on a CMOS Silicon on
Sapphire (SOS) process, which provides an immunity to
Single Event Latch-up and the capability of highly reliable
performance in any radiation environment. These devices
offer significant power reduction and faster performance
when compared to ALSTTL types.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
Detailed Electrical Specifications for the ACS174MS are
contained in SMD 5962-98634. A “hot-link” is provided
on our homepage for downloading.
http://www.intersil.com/spacedefense/spaceselect.htm
Ordering Information
ORDERING NUMBER
5962F9863401VCC
ACS174D/SAMPLE-03
5962F9863401VXC
ACS174K/SAMPLE-03
5962F9863401V9A
INTERNAL MARKETING
NUMBER
ACS174DMSR-03
ACS174D/SAMPLE-03
ACS174KMSR-03
ACS174K/SAMPLE-03
ACS174HMSR-03
Pinouts
ACS174MS
(SBDIP)
TOP VIEW
MR 1
Q0 2
D0 3
D1 4
Q1 5
D2 6
Q2 7
GND 8
16 VCC
15 Q5
14 D5
13 D4
12 Q4
11 D3
10 Q3
9 CP
Features
• QML Qualified Per MIL-PRF-38535 Requirements
• 1.25 Micron Radiation Hardened SOS CMOS
• Radiation Environment
- Latch-Up Free Under Any Conditions
- Total Dose (Max.) . . . . . . . . . . . . . . . . . 3 x 105 RAD(Si)
- SEU Immunity . . . . . . . . . . . . . <1 x 10-10 Errors/Bit/Day
- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm2)
• Input Logic Levels. . . . VIL = (0.3)(VCC), VIH = (0.7)(VCC)
• Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . ±12mA (Min)
• Quiescent Supply Current . . . . . . . . . . . . . . . 10µA (Max)
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 23ns (Max)
Applications
• High Speed Control Circuits
• Sensor Monitoring
• Low Power Designs
TEMP. RANGE (oC)
-55 to 125
25
-55 to 125
25
25
PACKAGE
16 Ld SBDIP
16 Ld SBDIP
16 Ld Flatpack
16 Ld Flatpack
Die
DESIGNATOR
CDIP2-T16
CDIP2-T16
CDFP4-F16
CDFP4-F16
NA
MR
Q0
D0
D1
Q1
D2
Q2
GND
ACS174MS
(FLATPACK)
TOP VIEW
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VCC
Q5
D5
D4
Q4
D3
Q3
CP
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

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