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PDF A6810 Data sheet ( Hoja de datos )
| Número de pieza | A6810 | |
| Descripción | 10-Bit Serial Input Latched Source Driver | |
| Fabricantes | Allegro MicroSystems | |
| Logotipo |  |
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A6810
10-Bit Serial Input Latched Source Driver
Features and Benefits
▪ Controlled output slew rate
▪ High-speed data storage
▪ 60 V minimum output breakdown
▪ High data-input rate
▪ PNP active pull-downs
▪ Low output-saturation voltages
▪ Low-power CMOS logic and latches
▪ Improved replacements for TL4810x, UCN5810x, and
UCQ5810x
Packages:
18-pin DIP
(A package)
Not to scale
20-pin SOICW
(LW package)
Description
The A6810 combines 10-bit CMOS shift registers,
accompanying data latches, and control circuitry with bipolar
sourcing outputs and PNP active pull-downs. Designed
primarily to drive vacuum-fluorescent (VF) displays, the 60 V
and –40 mA output ratings also allow this device to be used in
many other peripheral power driver applications. The A6810
features an increased data input rate (compared with the older
UCN/UCQ5810-F) and a controlled output slew rate.
The CMOS shift register and latches allow direct interfacing
with microprocessor-based systems. With a 3.3 or 5 V logic
supply, serial data-input rates of at least 10 MHz can be
attained
A CMOS serial data output permits cascaded connections in
applications requiring additional drive lines. Similar devices
are available as the A6812 (20-bit) and A6818 (32-bit).
TheA6810 output source drivers are NPN Darlingtons, capable
of sourcing up to 40 mA.The controlled output slew rate reduces
electromagnetic noise, which is an important consideration in
systems that include telecommunications and microprocessors,
and to meet government emissions regulations. For inter-digit
Continued on the next page…
Functional Block Diagram
26182.124I
1 page  
A6810
10-Bit Serial Input Latched Source Driver
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
CLOCK
50%
SERIAL
DATA IN
SERIAL
DATA OUT
AB
DATA
50%
t p(CH-SQX)
50%
D
E
DATA
STROBE
50%
BLANKING
OUT N
LOW = ALL OUTPUTS ENABLED
tp(STH-QH)
tp(STH-QL)
90%
DATA
10%
BLANKING
OUT N
Dwg. WP-029
HIGH = ALL OUTPUTS BLANKED (DISABLED)
50%
t en(BQ)
t dis(BQ)
tr
DATA
10%
tf
90%
50%
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) ........................................... 25 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) ................................................ 25 ns
C. Clock Pulse Width, tw(CH) ................................................. 50 ns
D. Time Between Clock Activation and Strobe, tsu(C) ......... 100 ns
E. Strobe Pulse Width, tw(STH) .............................................. 50 ns
NOTE – Timing is representative of a 10 MHz clock. Higher
speeds may be attainable; operation at high temperatures will
reduce the specified maximum clock frequency.
Serial Data present at the input is transferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
data information towards the SERIAL DATA OUTPUT. The
Dwg. WP-030A
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
Information present at any register is transferred to the
respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the
BLANKING input be high during serial data entry.
When the BLANKING input is high, the output source
drivers are disabled (OFF); the PNP active pull-down sink
drivers are ON. The information stored in the latches is not
affected by the BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of their respective
latches.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet A6810.PDF ] | |
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