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PDF A6595KA Data sheet ( Hoja de datos )
| Número de pieza | A6595KA | |
| Descripción | 8-BIT SERIAL-INPUT/ DMOS POWER DRIVER | |
| Fabricantes | Allegro MicroSystems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de A6595KA (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
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6595
ADVANCE INFORMATION
(Subject to change without notice)
January 24, 2000
POWER
GROUND
LOGIC
SUPPLY
SERIAL
DATA IN
1
2
3
OUT 0 4
VDD
OUT1 5
OUT 2 6
OUT 3 7
REGISTER 8
CLEAR
OUTPUT
ENABLE
POWER
GROUND
9
10
CLR
OE
20
POWER
GROUND
19
LOGIC
GROUND
18
SERIAL
DATA OUT
17 OUT7
16 OUT6
15 OUT5
14 OUT 4
CLK 13 CLOCK
ST 12 STROBE
11 POWER
GROUND
Dwg. PP-029-13
Note that the A6595KA (DIP) and the A6595KLW (SOIC)
are electrically identical and share a common terminal
number assignment.
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Output Voltage, VO ............................... 50 V
Output Drain Current,
Continuous, IO .......................... 250 mA*
Peak, IOM ................................. 750 mA*†
Peak, IOM ....................................... 2.0 A†
Single-Pulse Avalanche Energy,
EAS ................................................. 75 mJ
Logic Supply Voltage, VDD .................. 7.0 V
Input Voltage Range,
VI ................................... -0.3 V to +7.0 V
Package Power Dissipation,
PD ........................................... See Graph
Operating Temperature Range,
TA ................................. -40°C to +125°C
Storage Temperature Range,
TS ................................. -55°C to +150°C
* Each output, all outputs on.
† Pulse duration ≤ 100 µs, duty cycle ≤ 2%.
Caution: These CMOS devices have input static
protection (Class 3) but are still susceptible to damage if
exposed to extremely high static electrical charges.
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
The A6595KA and A6595KLW combine an 8-bit CMOS shift
register and accompanying data latches, control circuitry, and DMOS
power driver outputs. Power driver applications include relays, sole-
noids, and other medium-current or high-voltage peripheral power
loads.
The serial-data input, CMOS shift register and latches allow direct
interfacing with microprocessor-based systems. Serial-data input rates
are over 5 MHz. Use with TTL may require appropriate pull-up
resistors to ensure an input logic high.
A CMOS serial-data output enables cascade connections in appli-
cations requiring additional drive lines. Similar devices with reduced
rDS(on) are available as the A6A595.
The A6595 DMOS open-drain outputs are capable of sinking up to
750 mA. All of the output drivers are disabled (the DMOS sink drivers
turned off) by the OUTPUT ENABLE input high.
The A6595KA is furnished in a 20-pin dual in-line plastic package.
The A6595KLW is furnished in a wide-body, small-outline plastic
package (SOIC) with gull-wing leads. Copper lead frames, reduced
supply current requirements, and low on-state resistance allow both
devices to sink 150 mA from all outputs continuously, to ambient
temperatures over 85°C.
FEATURES
I 50 V Minimum Output Clamp Voltage
I 250 mA Output Current (all outputs simultaneously)
I 1.3 Ω Typical rDS(on)
I Low Power Consumption
I Replacements for TPIC6595N and TPIC6595DW
Always order by complete part number:
Part Number
A6595KA
A6595KLW
Package
20-pin DIP
20-lead SOIC
RθJA
55°C/W
70°C/W
RθJC
25°C/W
17°C/W
1 page  
6595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
CLOCK
SERIAL
DATA IN
SERIAL
DATA OUT
STROBE
OUTPUT
ENABLE
OUT N
OUTPUT
ENABLE
OUT N
C
50%
AB
DATA
50%
tp
50%
D
E
50%
DATA
LOW = ALL OUTPUTS ENABLED
t p HIGH = OUTPUT OFF
50% DATA
LOW = OUTPUT ON
Dwg. WP-029-2
HIGH = ALL OUTPUTS DISABLED
50%
t PHL
t PLH
tf
90%
DATA
tr
10%
Dwg. WP-030-2
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) .......................................... 10 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) .............................................. 10 ns
C. Clock Pulse Width, tw(CLK) ............................................. 20 ns
D. Time Between Clock Activation
and Strobe, tsu(ST) ....................................................... 50 ns
E. Strobe Pulse Width, tw(ST) .............................................. 50 ns
F. Output Enable Pulse Width, tw(OE) ................................ 4.5 µs
NOTE – Timing is representative of a 12.5 MHz clock.
Higher speeds are attainable.
Serial data present at the input is transferred to the shift
register on the rising edge of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information
towards the SERIAL DATA OUTPUT.
Information present at any register is transferred to the
respective latch on the rising edge of the STROBE input pulse
(serial-to-parallel conversion).
When the OUTPUT ENABLE input is high, the output
source drivers are disabled (OFF). The information stored in the
latches is not affected by the OUTPUT ENABLE input. With
the OUTPUT ENABLE input low, the outputs are controlled by
the state of their respective latches.
www.allegromicro.com
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet A6595KA.PDF ] | |
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