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PDF A62S8308V-70SI Data sheet ( Hoja de datos )
| Número de pieza | A62S8308V-70SI | |
| Descripción | 256K X 8 BIT LOW VOLTAGE CMOS SRAM | |
| Fabricantes | AMIC Technology | |
| Logotipo |  |
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A62S8308 Series
Preliminary
256K X 8 BIT LOW VOLTAGE CMOS SRAM
Document Title
256K X 8 BIT LOW VOLTAGE CMOS SRAM
Revision History
Rev. No.
0.0
0.1
0.2
History
Initial issue
Modify VCCmax from 3.3V to 3.6V
Add 55ns grade spec. for VCC = 3.0V to 3.6V
Issue Date
December 6, 1999
December 20, 2000
March 23, 2001
Remark
Preliminary
PRELIMINARY (March, 2001, Version 0.2)
AMIC Technology, Inc.
1 page  
A62S8308 Series
DC Electrical Characteristics (continued)
Symbol
Parameter
A62S8308-55S/70S
Min.
Max.
A62S8308-55SI/70SI
Min.
Max.
Unit
Conditions
ISB - 0.5 - 0.5 mA CE1 = VIH or
CE2 = VIL
ISB1 Standby Power
Supply Current
CE1 ≥ VCC - 0.2V
- 10 - 15 µA CE2 ≥ VCC - 0.2V
VIN ≥ 0V
ISB2
- 10
-
15
µA
CE2 ≤ 0.2V
VIN ≥ 0V
VOL Output Low Voltage
-
0.4
-
0.4 V IOL = 2.1mA
VOH Output High Voltage
2.4
-
2.4
- V IOH = -1.0mA
Truth Table
Mode
Standby
Output Disable
Read
Write
Note: X = H or L
CE1 CE2
HX
XL
LH
LH
LH
OE
X
X
H
L
X
WE
X
X
H
H
L
I/O Operation
High Z
High Z
High Z
DOUT
DIN
Supply Current
ISB, ISB1
ISB, ISB2
ICC, ICC1, ICC2
ICC, ICC1, ICC2
ICC, ICC1, ICC2
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
Parameter
Min.
CIN* Input Capacitance
CI/O*
Input/Output Capacitance
* These parameters are sampled and not 100% tested.
Max.
6
8
Unit
pF
pF
Conditions
VIN = 0V
VI/O = 0V
PRELIMINARY (March, 2001, Version 0.2)
4
AMIC Technology, Inc.
5 Page 
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5 ns
1.5V
See Figures 1 and 2
A62S8308 Series
TTL TTL
CL
30pF
CL
5pF
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for tCLZ1,
tCLZ2, tOHZ, tOLZ, tCHZ1,
tCHZ2, tWHZ, and tOW
Data Retention Characteristics (TA = 0°C to + 70°C or -25°C to 85°C)
Symbol
Parameter
Min. Max. Unit
Conditions
VDR1
2.0 3.6
V CE1 ≥ VCC - 0.2V
VDR2
VCC for Data Retention
2.0 3.6
CE2 ≤ 0.2V
V CE1 ≥ VCC - 0.2V or
CE1 ≤ 0.2V
ICCDR1
Data Retention Current
ICCDR2
S-Version
SI-Version
S-Version
SI-Version
- 5*
VCC = 2.0V
µA CE1 ≥ VCC - 0.2V
- 10**
CE2 ≥ VCC - 0.2V
VIN ≥ 0V
- 5*
VCC = 2.0V
µA CE2 ≤ 0.2V
- 10**
VIN ≥ 0V
tCDR Chip Disable to Data Retention Time
0
tR Operation Recovery Time
tRC
* A62S8308-55S/70S
** A62S8308-55SI/70SI
ICCDR: Max. 1µA at TA = 0°C + 40°C
ICCDR: Max. 1µA at TA = 0°C + 40°C
-
-
ns
See Retention Waveform
ns
PRELIMINARY (March, 2001, Version 0.2)
10
AMIC Technology, Inc.
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet A62S8308V-70SI.PDF ] | |
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