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PDF ACT-F512K8N-090F6T Data sheet ( Hoja de datos )
| Número de pieza | ACT-F512K8N-090F6T | |
| Descripción | ACT-F512K8 High Speed 4 Megabit Monolithic FLASH | |
| Fabricantes | Aeroflex Circuit Technology | |
| Logotipo |  |
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ACT–F512K8 High Speed
4 Megabit Monolithic FLASH
Features
CIRCUIT TECHNOLOGY
www.aeroflex.com
s Low Power Monolithic 512K x 8 FLASH
s Industry Standard Pinouts
s TTL Compatible Inputs and CMOS Outputs s Packaging – Hermetic Ceramic
s Access Times of 60, 70, 90, 120 and 150ns
s +5V Programing, 5V ±10% Supply
s 100,000 Erase / Program Cycles
s Low Standby Current
q 32 Lead, 1.6" x .6" x .20" Dual-in-line Package (DIP),
Aeroflex code# "P4"
q 32 Lead, .82" x .41" x .11" Ceramic Flat Package
(FP), Aeroflex code# "F6"
q 32 Lead, .82" x .41" x .132" Ceramic Flat Package
(FP Lead Formed), Aeroflex code# "F7"
s Page Program Operation and Internal
Program Control Time
s Supports Full Chip Erase
s Sector Architecture
q 8 Equal size sectors of 64K bytes each
q Any Combination of Sectors ccan be erased with one
command sequence.
s Embedded Erase and Program Algorithms s Commercial, Industrial and Military
s Supports Full Chip Erase
Temperature Ranges
s
MIL-PRF-38534 Compliant Circuits Available
s
DESC SMD Pending
5962-96692 (P4,F6,F7)
Block Diagram – DIP (P4) & Flat Packages (F6,F7)
WE
OE
A0 – A18
CE
Vss
512Kx8
Vcc
8
I/O0-7
Pin Description
I/O0-7
Data I/O
A0–18 Address Inputs
WE Write Enable
CE Chip Enable
OE Output Enable
VCC Power Supply
VSS Ground
NC Not Connected
General Description
The ACT–F512K8 is a high
speed, 4 megabit CMOS
monolithic Flash module
designed for full temperature
range military, space, or high
reliability applications.
This device is input TTL and
output CMOS compatible. The
command register is written by
bringing WE to a logic low level
(VIL), while CE is low and OE is
at logic high level (VIH). Reading
is accomplished by chip Enable
(CE) and Output Enable (OE)
being logically active, see
Figure 9. Access time grades of
60ns, 70ns, 90ns, 120ns and
150ns maximum are standard.
The ACT–F512K8 is
available in a choice of
eroflex Circuit Technology - Advanced Multichip Modules © SCD1668 REV A 4/28/98
1 page  
Device Operation
The ACT–F512K8 Monolithic is composed of One, Four
megabit flash device. Programming of the ACT–F512K8
is accomplished by executing the program command
sequence. The program algorithm, which is an internal
algorithm, automatically times the program pulse widths
and verifies proper cell status. Sectors can be pro-
gramed and verified in less than 1 second. Erase is
accomplished by executing the erase command
sequence. The erase algorithm, which is internal, auto-
matically preprograms the array if it is not already pro-
gramed before executing the erase operation. During
erase, the device automatically times the erase pulse
widths and verifies proper cell status. The entire mem-
ory is typically erased and verified in 1.5 seconds (if
pre-programmed). The sector mode allows for 64K byte
blocks of memory to be erased and reprogrammed with-
out affecting other blocks.
Bus Operation
READ
The ACT–F512K8 has two control functions, both of
which must be logically active, to obtain data at the out-
puts. Chip Enable (CE) is the power control and should
be used for device selection. Output-Enable (OE) is the
output control and should be used to gate data to the
output pins of the chip selected. Figure 7 illustrates AC
read timing waveforms.
OUTPUT DISABLE
With Output-Enable at a logic high level (VIH), output
from the device is disabled. Output pins are placed in a
high impedance state.
STANDBY MODE
The ACT-F512K8 standby mode consumes less than 6.5
mA. In the standby mode the outputs are in a high
impedance state, independent of the OE input. If the
device is deselected during erasure or programming, the
device will draw active current until the operation is com-
pleted.
WRITE
Device erasure and programming are accomplished via
the command register. The contents of the register
serve as input to the internal state machine. The state
machine outputs dictate the function of the device.
The command register itself does not occupy an addres-
sable memory location. The register is a latch used to
store the command, along with address and data infor-
mation needed to execute the command. The command
register is written by bringing WE to a logic low level
(VIL), while CE is low and OE is at VIH. Addresses are
latched on the falling edge of WE or CE, whichever hap-
pens later. Data is latched on the rising edge of the WE
or CE whichever occurs first. Standard microprocessor
write timings are used. Refer to AC Program Character-
istics and Waveforms, Figures 3, 8 and 13.
Command Definitions
Device operations are selected by writing specific
address and data sequences into the command register.
Table 3 defines these register command sequences.
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command regis-
ter. Microprocessor read cycles retrieve array data from
the memory. The device remains enabled for reads until
the command register contents are altered.
The device will automatically power-up in the read/reset
state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will
retrieve array data. The device will automatically
power-up in the read/reset state. In this case, a com-
mand sequence is not required to read data. Standard
Microprocessor read cycles will retrieve array data. This
default value ensures that no spurious alteration of the
memory content occurs during the power transition.
Refer to the AC Read Characteristics and Figure 7 for
the specific timing parameters.
BYTE PROGRAMING
The device is programmed on a byte-byte basis. Pro-
gramming is a four bus cycle operation. There are two
"unlock" write cycles. These are followed by the program
Table 1 – Bus Operations
Operation
CE OE WE A0 A1 A9 I/O
READ
L L H A0 A1 A9 DOUT
STANDBY
H X X X X X HIGH Z
OUTPUT DISABLE L H H X X X HIGH Z
WRITE
L H L A0 A1 A9 DIN
ENABLE SECTOR
PROTECT
L VID L
X
X VID
X
VERIFY SECTOR
PROTECT
L
L
H
L
H VID Code
Aeroflex Circuit Technology
5
Table 2 – Sector Addresses Table
A16 A15 A14
SA0 0 0 0
SA1 0 0 1
SA2 0 1 0
SA3 0 1 1
SA4 1 0 0
SA5 1 0 1
SA6 1 1 0
SA7 1 1 1
Address Range
00000h – 03FFFh
04000h – 07FFFh
08000h – 0BFFFh
0C000h – 0FFFFh
10000h – 13FFFh
14000h – 17FFFh
18000h – 1BFFFh
1C000h – 1FFFFh
SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700
5 Page 
Figure 4
Erase Algorithm
Bus
Operations
Standby
Write
Read
Standby
Command
Sequence
Comments
Program
Valid Address/Data Sequence
Data Polling to Verify Programming
Compare Data Output to Data Expected
Start
Write Erase Command Sequence
(See Below)
Data Poll or Toggle Bit
Successfully Completed
Erasure Completed
Chip Erase Command Sequence
(Address/Command)
5555H/AAH
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command)
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/80H
5555H/80H
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/10H
Sector Address/30H
Additional Sector
Erase Commands
are Optional
Sector Address/30H
Sector Address/30H
Aeroflex Circuit Technology
11 SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700
11 Page | ||
| Páginas | Total 21 Páginas | |
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