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PDF ACT-E128K32C-250P3T Data sheet ( Hoja de datos )
| Número de pieza | ACT-E128K32C-250P3T | |
| Descripción | ACT-E128K32 High Speed 4 Megabit EEPROM Multichip Module | |
| Fabricantes | Aeroflex Circuit Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ACT-E128K32C-250P3T (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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ACT–E128K32 High Speed
4 Megabit EEPROM Multichip Module
Features
CIRCUIT TECHNOLOGY
www.aeroflex.com
■ 4 Low Power 128K x 8 EEPROM Die in One MCM
Package
■ Organized as 128K x 32
● User Configurable to 256K x 16 or 512K x 8
■ CMOS and TTL Compatible Inputs and Outputs
■ Access Times of 120,140,150, 200, 250& 300ns
■ +5V ±10% Supply
■ Automatic Page Write Operation
■ Page Write Cycle Time: 10ms Max
■ Data Retention Ten Years Minimum
■ Low Power CMOS
■ Data Polling for End of Write Detection
■ Industry Standard Pinouts
■ Packaging – Hermetic Ceramic
● 66 Pin, 1.08" x 1.08" x .160" PGA Type, No Shoulder,
Aeroflex code# "P3"
● 66 Pin, 1.08" x 1.08" x .185" PGA Type, With
Shoulder, Aeroflex code# "P7"
● 68 Lead, .88" x .88" x .200" Dual-Cavity Small
Outline Gull Wing, Aeroflex code# "F2" (Drops into
the 68 Lead JEDEC .99"SQ CQFJ footprint)
■ MIL-PRF-38534 Compliant MCMs Available
■ Hardware and Software Data Protection
■ Internal Decoupling Capacitors for Low Noise
Operation
■ Commercial, Industrial and Military Temperature
Ranges
■ SMD# 5962–94585 Released (P7 & F2)
General Description
Block Diagram – PGA Type Package (P3,P7) & CQFP (F2)
WE1 CE1 WE2 CE2 WE3 CE3 WE4 CE4
A0 – A16
OE
128Kx8 128Kx8 128Kx8 128Kx8
8
I/O0-7
88
8
I/O8-15 I/O16-23 I/O24-31
Pin Description
I/O0-31 Data I/O
A0–16 Address Inputs
WE1-4 Write Enables
OE Output Enable
CE1-4 Chip Enables
VCC Power Supply
GND
Ground
The ACT–E128K32 is a high
speed, 4 megabit, CMOS
EEPROM multichip module
(MCM) designed for full
temperature range military,
space, or high reliability
applications. The MCM can be
organized as a 256K x 16 bits
or 512K x 8 bits device and is
input and output CMOS and
TTL compatible. Writing is
executed when the write enable
(WE) and chip enable (CE)
inputs are low and output
enable (OE) is high. Reading is
accomplished when WE is high
and CE and OE are both low.
Access times grades of
120, 140, 150, 200, 250 & 300ns
are standard.
The ACT–E128K32 is
packaged in a choice of
hermetically sealed co-fired
ceramic packages, a 66 pin,
1.08" sq PGA or a 68 lead, .88"
sq gullwing CQFP. The device
operates over the temperature
range of -55°C to +125°C and
military environment.
eroflex Circuit Technology - Advanced Multichip Modules © SCD1662 REV B 9/5/01
1 page  
The usual procedure is to increment the least
significant address lines from A0 through A6
at each write cycle. In this manner a page of
up to 128 bytes can be loaded in to the
EEPROM in a burst mode before beginning
the relatively long interval programming
cycle.
After the tBLC time out is completed, the
EEPROM begins an internal write cycle.
During this cycle the entire page will be
written at the same time. The internal
programming cycle is the same regardless of
the number of bytes accessed.
SOFTWARE DATA PROTECTION
A software write protection feature may be
enabled or disabled by the user. When
shipped by Aeroflex Microelectronics, the
ACT-E128K32 has the feature disabled.
Write access to the device is unrestricted.
To enable software write protection, the user
writes three access code bytes to three
special internal locations. Once write
protection has been enabled, each write to
the EEPROM must use the same three byte
write sequence to permit writing. The write
protection feature can be disabled by a six
byte write sequence of specific data to
specific locations. Power transitions will not
reset the software write protection.
Each 128K byte block of the EEPROM has
independent write protection. One or more
blocks may be enabled and the rest disabled
in any combination. The software write
protection guards against inadvertent writes
during power transitions, or unauthorized
modification using a PROM programmer.
HARDWARE DATA PROTECTION
These features protect against inadvertent
writes to the ACT-E128K32. These are
included to improve reliability during normal
operation:
A) Vcc Sense
While below 3.8V typical write cycles
are inhibited.
B) Write inhibiting
Holding OE low and either CE or WE
high inhibits write cycles.
C) Noise filter
Pulses of <10ns (TYP) on WE or CE
will not initiate a write cycle.
A
Aeroflex Circuit Technology
5 SCD1662 REV B 9/5/01 Plainview NY (516) 694-6700
5 Page 
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Function
GND
CE3
A5
A4
A3
A2
A1
A0
NC
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Pin Numbers & Functions
68 Pins — Dual-Cavity CQFP
Pin #
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Function
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
Vcc
A11
A12
A13
A14
A15
A16
CE1
Pin #
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Function
OE
CE2
NC
WE2
WE3
WE4
NC
NC
NC
I/O31
I/O30
I/O29
I/O28
I/O27
I/O26
I/O25
I/O24
Pin #
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Function
GND
I/O23
I/O22
I/O21
I/O20
I/O19
I/O18
I/O17
I/O16
VCC
A10
A9
A8
A7
A6
WE1
CE4
Package Outline — Dual-Cavity CQFP "F2"
Top View
Pin 10
Pin 9
.990 SQ
±.010
.880 SQ
±.010
Pin 61
Pin 60
.015
±.010
Pin 26
Pin 27
.800 REF
All dimensions in inches
.050
TYP
Pin 44
Pin 43
*.200 MAX
.010 REF
.946
±.010
0°- 7°
0.010 R
.040
.010 ±.005
Detail “A”
See Detail “A”
*.180 MAX available, call factory for details
Aeroflex Circuit Technology
11 SCD1662 REV B 9/5/01 Plainview NY (516) 694-6700
A
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ACT-E128K32C-250P3T.PDF ] | |
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