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ACT-5271PC-200F17M fiches techniques PDF

Aeroflex Circuit Technology - ACT5271 64-Bit Superscaler Microprocessor

Numéro de référence ACT-5271PC-200F17M
Description ACT5271 64-Bit Superscaler Microprocessor
Fabricant Aeroflex Circuit Technology 
Logo Aeroflex Circuit Technology 





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ACT-5271PC-200F17M fiche technique
ACT5271
64-Bit Superscaler Microprocessor
Features
s Full militarized QED RM5271 microprocessor
s Dual Issue superscalar microprocessor - can issue one
integer and one floating-point instruction per cycle
q 150, 200, 250 MHz operating frequencies – Consult Factory for
latest speeds
q 345 Dhrystone2.1 MIPS maximum
q SPECInt95 7.3, SPECfp95 8.3 maximum
s High performance system interface compatible with RM7000,
RM5270, RM5260, RM5261, R4600, R4700 and R5000
q Up to 125MHz memory bus operation for a 1000MBps bandwidth
from CPU to L2 cache and main memory
q 64-bitmultiplexed system address/data bus for optimum price/
performance with high performance write protocols to maximize
uncached write bandwidth
q Supports 1/2 clock divisors (2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9)
q IEEE 1149.1 JTAG boundary scan
s Integrated on-chip caches
q 32KB/32KB instruction/data -both 2 way set associative
q Virtually indexed, physically tagged
q Write-back and write-through on per page basis
q Pipeline restart on first double for data cache misses
s Integrated secondary cache controller (R5000 compatible)
q Supports 512K or 2MByte block write-through secondary
s Integrated memory management unit
q Fully associative joint TLB (shared by I and D translations)
q 48 dual entries map 96 pages
q Variable page size (4KB to 16MB in 4x increments)
s High-performance floating point unit - up to 532 MFLOPS
q Single cycle repeat rate for common single precision operations
and some double precision operations
q Two cycle repeat rate for double precision multiply and double
precision combined multiply-add operations
q Single cycle repeat rate for single precision combined multiply-
add operation
s MIPS IV instruction set
q Floating point multiply-add instruction increases performance in
signal processing and graphics applications
q Conditional moves to reduce branch frequency
q Index address modes (register + register)
s Embedded application enhancements
q Specialized DSP integer Multiply-Accumulate instruction and 3
operand multiply instruction
q I and D cache locking by set
q Optional dedicated exception vector for interrupts
s Fully static CMOS design with power down logic
q Standby reduced power mode with WAIT instruction
q 4.2 Watts typical power @ 200MHz
q 2.5V core with 3.3V IO’s
s 208-lead CQFP, cavity-up package (F17)
s 208-lead CQFP, inverted footprint (F24), Intended to duplicate
the commercial QED footprint
s 179-pin PGA package (Future Product) (P10)
BLOCK DIAGRAM
Preliminary
eroflex Circuit Technology – RISC TurboEngines For The Future © SCD5271 REV 1 12/22/98

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