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PDF AD28MSP01 Data sheet ( Hoja de datos )
| Número de pieza | AD28MSP01 | |
| Descripción | PSTN Signal Port | |
| Fabricantes | Analog Devices | |
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a
PSTN Signal Port
AD28msp01
FEATURES
Complete Analog l/O Port for DSP-Based FAX/MODEM
Applications
Linear-Coded 16-Bit Sigma-Delta ADC
Linear-Coded 16-Bit Sigma-Delta DAC
On-Chip Anti-Alias and Anti-lmage Filters
Digital Resampling/lnterpolation Filter
7.2 kHz, 8.0 kHz, and 9.6 kHz Sampling Rates
8/7 Mode for 8.23 kHz, 9.14 kHz, and 10.97 kHz
Sampling Rates
Synchronous and Asynchronous DAC/ADC Modes
Bit and Baud Clock Generation
Transmit Digital Phase-Locked Loop for Terminal
Synchronization
Independent Transmit and Receive Phase Adjustment
Serial Interface to DSP Processors
+5 V Operation with Power-Down Mode
28-Pin Plastic DlP/44-Lead PLCC/28-Lead SOIC
APPLICATIONS
High Performance DSP-Based Modems
V.32ter, V.32bis, V.32, V.22bis, V.22, V.21,
Bell 212A, 103
Fax and Cellular-Compatible Modems
V.33, V.29, V.27ter, V.27bis, V.27, V.26bis
Integrated Fax, Modem, and Speech Processing
FUNCTIONAL BLOCK DIAGRAM
ANALOG
INPUTS
16-BIT
SIGMA-DELTA
ADC
VOLTAGE
REFERENCE
RESAMPLING
INTERPOLATION
FILTER
SERIAL
PORT
DIGITAL
DATA AND
CONTROL
DIFFERENTIAL
ANALOG
OUTPUT
16-BIT
SIGMA-DELTA
DAC
CLOCK INPUTS
CLOCK OUTPUTS
CLOCK
GENERATION
GENERAL DESCRIPTION
The AD28msp01 is a complete analog front end for high perfor-
mance DSP-based modems. The device includes all data conver-
sion, filtering, and clock generation circuitry needed to imple-
ment an echo-cancelling modem with a single host digital signal
processor. Software-programmable sample rates and clocking
modes support all established modem standards. The AD28msp01
simplifies overall system design by requiring only +5 volts.
The inclusion of on-chip anti-aliasing and anti-imaging filters
and 16-bit sigma-delta ADC and DAC ensures a highly inte-
grated and compact solution for FAX or data MODEM applica-
tions. Sigma-delta conversion technology eliminates the need for
complex off-chip anti-aliasing filters and sample-and-hold circuitry.
The AD28msp01 utilizes advanced sigma-delta technology to
move the entire echo-cancelling modem implementation into the
digital domain. The device maintains a –72 dB SNR throughout
all filtering and data conversion. Purely DSP-based echo cancel-
lation algorithms can thereby maintain robust bit error rates
under worst-case signal attenuation and echo amplitude condi-
tions. The AD28msp01’s on-chip interpolation filter resamples
the received signal after echo cancellation in the DSP, freeing
the processor for other voice or data communications tasks.
On-chip bit and baud clock generation circuitry provides for
either synchronous or asynchronous operation of the transmit
(DAC) and receive (ADC) paths. Each path features indepen-
dent phase advance and retard adjustments via software control.
The AD28msp01 can also synchronize modem operation to an
external terminal bit clock.
The AD28msp01’s serial I/O port provides an easy interface to
host DSP microprocessors such as the ADSP-2101, ADSP-2105,
and ADSP-2111. Packaged in a 28-pin plastic DIP, 44-lead
PLCC, 44-pin TQFP, or 28-lead SOIC, the AD28msp01 pro-
vides a compact solution for space-constrained environments.
The device operates from a +5 V supply and offers a low power
sleep mode for battery-powered systems.
A detailed block diagram of the AD28msp01 is shown in
Figure 1.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
REV. A
AD28msp01
{This ADSP-2101 program initializes the AD28msp01}
{and executes a loopback, or talk-through, routine.}
. MODULE/RAM/BOOT = 0 MSP01;
. VAR/DM/CIRC rec[2];
. VAR/DM/CIRC trans[2];
rset:
irq2v:
sprt0t:
sprt0r:
sprt1t:
sprt1r:
timerv:
JUMP start;
RTI; RTI; RTI;
RTI; RTI; RTI; RTI;
AX0 = 0x25; DM(0x3ff3) = AX0;
RTI; RTI;
JUMP receive;
RTI; RTI; RTI;
RTI; RTI; RTI; RTI;
RTI; RTI; RTI; RTI;
RTI; RTI; RTI; RTI;
start:
init dsp:
init msp01:
initi:
wait:
receive:
I2 = ^re c ;
L2 = %rec;
I3 = ^trans;
L3 = %trans;
M0 = 0;
M1 = 1;
S1 = 0;
DM(0x3000) = SI;
AX0 = 0x2a0f;
DM(0x3ff6) = AX0;
AX0 = 0x101f;
DM(0x3fff) = AX0;
IMASK = 0x10;
AR = 0;
CNTR = 6;
DO initi UNTIL CE;
TX0 = AR;
IDLE;
TX0 = SI;
IDLE;
AY0 = AR;
AR = AY0 +1;
AX1 = 1;
AR = 0x18;
TX0 = AX1;
IDLE;
TX0 = AR;
AR = B#0025;
DM(0x3ff3) = AR;
IMASK = 0x18;
JUMP wait;
DM(0x3ff3) = SI;
AX1= DM(I2, M1);
{Receive word buffer}
{Transmit word buffer}
{lnterrupt Vectors}
{Disable TX autobuffer}
{Initialize DAGs}
{Reset the AD28msp01}
{Initialize the ADSP-2101}
{Ext RFS, Int TfS, Ext SCLK, SLEN = 15}
{SPORT0 control register}
{Enable SPORT0}
{System control register}
{Initialize AD28msp01 control register}
{Note: This section could be autobuffered.}
{Enable SPORT0 TX interrupt}
{Transmit address}
{Transmit control word}
{Increment address}
{Power up AD28msp01}
{Enable RX autobuffering with I2, M1}
{Autobuffer control register}
{Enable RX and TX interrupt}
{Wait for receive interrupt}
{Receive Interrupt Routine}
{Disable autobuffering}
{Read first receive word from buffer}
–5–
5 Page 
AD28msp01
V.32 TSYNC Mode
In V.32 TSYNC Mode, shown in Figure 7, the AD28msp01’s
transmit circuitry is synchronized to an external TSYNC signal.
The AD28msp01 receive circuitry is sampled synchronous to
the transmit circuitry, but the data can be resampled at a differ-
ent phase by using the resampling interpolation filter.
TCONV, TBIT and TBAUD are generated internally but are
phase-locked to the external TSYNC input signal with the digi-
tal phase-locked loop. RCONV, RBIT and RBAUD are gener-
ated internally (but frequency locked to TSYNC) and can be
phase adjusted with the Receive Phase Adjust Register (Control
Register 4).
TCONV initiates a new DAC sample update, loads the ADC
register (Data Register 2), and loads the DAC register (Data
Register 0) with a new sample.
The digital resampling interpolation filter can be used for digital
resampling of the received signal. Enable this function by setting
Bit 9 in Control Register 0. The phase of the resampled signal is
adjusted with the Receive Phase Adjust Register. Samples are
loaded into the interpolator at the TCONV rate and are resampled
at the RCONV rate.
When entering V.32 TSYNC Mode, RCONV is locked to
TCONV before TCONV is locked to TSYNC. If this mode is
entered from a non-V.32 mode, the device performs a soft reset.
The time required to lock TCONV to RCONV is dependent on
the phase difference between RCONV and TCONV when en-
tering the mode.
This mode is entered by setting the Operating Mode field in
Control Register 0. The RCONV/TCONV rate can be set to
9.6 kHz, 8.0 kHz or 7.2 kHz by setting the sample rate bit field
in Control Register 0. The TBIT and TBAUD clock rates are
set by adjusting the appropriate bits in Control Register 3. The
RBIT and RBAUD clock rates are set by adjusting the appropri-
ate bits in Control Register 2. The bit rates, baud rates and
TSYNC rate can be set to any combination of clock rates listed
in the control register descriptions. The TSYNC field on Con-
trol Register 0 must be set to the frequency of the input pin.
Example
Transferring the following word sequence to the AD28msp01
will configure the device for V.32 TSYNC Mode at the clock
rates indicated:
Word
Transferred
Description
0x0000
0x0254
0x0002
0x0002
0x0003
0x0023
0x0001
0x0018
Control Register 0 address word
Enable interpolation filter, TSYNC = 7200,
sample rate = 7200, mode = V.32 TSYNC
Control Register 2 address word
RBAUD = 2400, RBIT = 7200
Control Register 3 address word
TBAUD = 1200, TBIT = 4800
Control Register 1 address word
Configure and power-up device
ANALOG IN
MCLK
TSYNC
ANALOG OUT
16
A/D
DATA
REGISTER 2
TX CLOCKS
TCONV
TBIT
TBAUD
PHASE ADJUST
CONVERT
START
DIGITAL PHASE
LOCKED LOOP
AD28msp01
16
RXRCXLCOLCOKCSKS
RCONV
RBIT
RBAUD
PHASE ADJUST
CONTROL
REGISTER 4
RX PHASE ADJUST
INTERPOLATION
FILTER
DATA
REGISTER 1
16
PHASE
ADJUST
16
DATA
REGISTER 3
16
D/A
DATA
REGISTER 0
16
DSP Processor
16 ECHO
CANCELLATION
16
TO MODEM RX
FROM MODEM TX
Figure 7. V.32 TSYNC Mode Block Diagram
REV. A
–11–
11 Page | ||
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| PDF Descargar | [ Datasheet AD28MSP01.PDF ] | |
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