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PDF AD261 Data sheet ( Hoja de datos )
| Número de pieza | AD261 | |
| Descripción | High Speed/ Logic Isolator | |
| Fabricantes | Analog Devices | |
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High Speed, Logic Isolator
AD261
FEATURES
Isolation Test Voltage: To 3.5 kV rms
Five Isolated Logic Lines: Available in Six I/O Configurations
Logic Signal Bandwidth: 20 MHz (min)
CMV Transient Immunity: 10 kV/s min
Waveform Edge Transmission Symmetry: ؎1 ns
Field and System Output Enable/Three-State Functions
Performance Rated Over –25؇C to +85؇C
UL1950, IEC950, EN60950 Certification (VDE, CE, Pending)
APPLICATIONS
PLC/DCS Analog Input and Output Cards
Communications Bus Isolation
General Data Acquisition Applications
IGBT Motor Drive Controls
High Speed Digital I/O Ports
GENERAL DESCRIPTION
The AD261 is designed to isolate five digital control signals
to/from a microcontroller and its related field I/O components.
Six models allow all I/O combinations from five input lines to
five output lines, including combinations in between. Every
AD261 effectively replaces up to five opto-isolators.
Each line of the AD261 has a bandwidth of 20 MHz (min) with
a propagation delay of only 14 ns, which allows for extremely
fast data transmission. Output waveform symmetry is maintained
to within ± 1 ns of the input so the AD261 can be used to accu-
rately isolate time-based PWM signals.
All field or system output pins of the AD261 can be set to a high
resistance three-state level by use of the two enable pins. A field
output three-stated offers a convenient method of presetting
logic levels at power-up by use of pull-up/down resistors. Sys-
tem side outputs being three-stated allows for easy multiplexing
of multiple AD261s.
The isolation barrier of the AD261 B Grade is 100% tested
as high as 3.5 kV rms (system to field). The barrier design also
provides excellent common-mode transient immunity from
10 kV/µs common-mode voltage excursions of field side termi-
nals relative to the system side, with no false output triggering
on either side.
Each output is updated within nanoseconds by input logic tran-
sitions, the AD261 also has a continuous output update feature
that automatically updates each output based on the dc level of
the input. This guarantees the output is always valid 10 µs after
a fault condition or after the power-up reset interval.
FUNCTIONAL BLOCK DIAGRAM
LATCH
F0
STTHARTEEE-
LINE 0
D
E
S0
LATCH
F1
STTHARTEEE-
LINE 1
D
E
2 S1
LATCH
F2
STTHARTEEE-
LINE 2
D
E
3 S2
LATCH
F3
D
E
LINE 3
THSRTAETEE-
4 S3
LATCH
F4
D
E
LINE 4
THSRTAETEE-
5 S4
ENABLEFLD 17
+5V dcFLD 16 +5V dc
5Vdc RTN
5V RTNFLD 15
6 ENABLESYS
+5V dc
7 +5V dcSYS
5Vdc RTN
8 5V RTNSYS
FIELD
SYSTEM
TYPICAL MODEL
(AD261-2)
PRODUCT HIGHLIGHTS
Six Isolated Logic Line I/O Configurations Available: The
AD261 is available in six pin-compatible versions of I/O con-
figurations to meet a wide variety of requirements.
Wide Bandwidth with Minimal Edge Error: The AD261
affords extremely fast isolation of logic signals due to its 20 MHz
bandwidth and 14 ns propagation delay. It maintains a wave-
form input-to-output edge transition error of typically less than
± 1 ns (total) for positive vs. negative transition.
3.5 kV rms Test Voltage Isolation Rating: The AD261
B Grade is rated to operate at 1.25 kV rms and is 100% pro-
duction tested at 3.5 kV rms, using a standard ADI test method.
High Transient Immunity: The AD261 rejects common-
mode transients slewing at up to 10 kV/µs without false trigger-
ing or damage to the device.
(Continued on page 5)
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1997
1 page  
AD261 CONFIGURATIONS
AD261
AD261-4
LATCH
F0
STTHARTEEE-
LINE 0
D
E
S0
LATCH
F1
D
E
LINE 1
THSRTAETEE-
2 S1
LATCH
F2
D
E
LINE 2
THSRTAETEE-
3 S2
LATCH
F3
D
E
LINE 3
THSRTAETEE-
4 S3
LATCH
F4
D
E
LINE 4
THSRTAETEE-
5 S4
ENABLEFLD 17
+5V dcFLD 16 +5V dc
5V dc RTN
5V RTNFLD 15
6 ENABLESYS
+5V dc
7 +5V dcSYS
5V dc RTN
8 5V RTNSYS
FIELD
SYSTEM
AD261-5
LATCH
F0
D
E
LINE 0
THSRTAETEE-
S0
LATCH
F1
D
E
LINE 1
THSRTAETEE-
2 S1
LATCH
F2
D
E
LINE 2
THSRTAETEE-
3 S2
LATCH
F3
D
E
LINE 3
THSRTAETEE-
4 S3
LATCH
F4
D
E
LINE 4
THSRTAETEE-
5 S4
ENABLEFLD 17
+5V dcFLD 16 +5V dc
5V dc RTN
5V RTNFLD 15
FIELD
6 ENABLESYS
+5V dc
7 +5V dcSYS
5V dc RTN
8 5V RTNSYS
SYSTEM
(Continued from page 1)
Field and System Enable Functions: Both the isolated and
nonisolated sides of the AD261 have ENABLE pins that three-
state all outputs. Upon reenabling these pins, all outputs are
updated to reflect the current input logic level.
CE Certifiable: Simply by adding the external bypass capacitors
at the supply pins, the AD261 can attain CE certification in
most applications (to the EMC directive) and conformance to
the low voltage (safety) directive is assured by the EN60950
certification.
Table I. Model Number and Pinout Function
Pin AD261-0 AD261-1 AD261-2 AD261-3 AD261-4 AD261-5
1 S0 (Xmt)
2 S1 (Xmt)
3 S2 (Xmt)
4 S3 (Xmt)
5 S4 (Xmt)
6 ENABLESYS
7 +5 V dcSYS
8 5 V RTNSYS
9–14
15 5 V RTNFLD
16 +5 V dcFLD
17 ENABLEFLD
18 F0 (Rcv)
19 F1 (Rcv)
20 F2 (Rcv)
21 F3 (Rcv)
22 F4 (Rcv)
S0 (Xmt) S0 (Xmt) S0 (Xmt) S0 (Xmt) S0 (Rcv)
S1 (Xmt) S1 (Xmt) S1 (Xmt) S1 (Rcv) S1 (Rcv)
S2 (Xmt) S2 (Xmt) S2 (Rcv) S2 (Rcv) S2 (Rcv)
S3 (Xmt) S3 (Rcv) S3 (Rcv) S3 (Rcv) S3 (Rcv)
S4 (Rcv) S4 (Rcv) S4 (Rcv) S4 (Rcv) S4 (Rcv)
* ** * *
* ** * *
* ** * *
Not Present
* **
*
* ** * *
* ** * *
F0 (Rcv) F0 (Rcv) F0 (Rcv) F0 (Rcv) F0 (Xmt)
F1 (Rcv) F1 (Rcv) F1 (Rcv) F1 (Xmt) F1 (Xmt)
F2 (Rcv) F2 (Rcv) F2 (Xmt) F2 (Xmt) F2 (Xmt)
F3 (Rcv) F3 (Xmt) F3 (Xmt) F3 (Xmt) F3 (Xmt)
F4 (Xmt) F4 (Xmt) F4 (Xmt) F4 (Xmt) F4 (Xmt)
*Pin function is the same on all models, as shown in the AD261-0 column.
GENERAL ATTRIBUTES
The AD261 provides five HCMOS compatible isolated logic
lines with ≥ 10 kV/µs common-mode transient immunity.
The case design and pin arrangement provides greater than
18 mm spacing between field and system side conductors, pro-
viding CSA/IS and IEC creepage spacing consistent with 750 V
mains isolation.
The five unidirectional logic lines have six possible combina-
tions of “ins” and “outs,” or transmitter/receiver pairs; hence
there are six AD261 part configurations (see Table I).
Each 20 MHz logic line has a Schmidt trigger input and a three-
state output (on the other side of the isolation barrier) and 14 ns of
propagation delay. A single enable pin on either side of the
barrier causes all outputs on that side to go three-state and all
inputs (driven pins) to ignore their inputs and retain their last
known state.
Note: All unused logic inputs (1–5) should be tied either high or low,
but not left floating.
Edge “fidelity,” or the difference in propagation time for rising
and falling edges, is typically less than ± 1 ns.
Power consumption, unlike opto-isolators, is a function of operat-
ing frequency. Each logic line barrier driver requires about 160 µA
per MHz and each receiver 40 µA per MHz plus, of course, 4 mA
total idle current (each side). The supply current diminishes
slightly with increasing temperature (about –0.03%/°C).
The total capacitance spanning the isolation barrier is less than
10 pF.
The minimum period of a pulse that can be accurately coupled
across the barrier is about 25 ns. Therefore the maximum
square-wave frequency of operation is 20 MHz.
REV. 0
–5–
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet AD261.PDF ] | |
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