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PDF AD1985 Data sheet ( Hoja de datos )
| Número de pieza | AD1985 | |
| Descripción | AC 97 SoundMAX Codec | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD1985 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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AC ’97 SoundMAX® Codec
AD1985
AC ’97 2.3 COMPLIANT FEATURES
6 DAC channels for 5.1 surround
Greater than 90 dB dynamic range
20-bit resolution on all DACs
S/PDIF Output
Integrated stereo headphone amplifiers
Variable rate audio
Double rate audio (fS = 96 kHz)
Line-level mono phone input
High quality CD mixer input
Selectable MIC input with preamp
AUX and line in stereo inputs
External amplifier power down (EAPD)
Power management modes
Jack sensing and peripheral enumeration/identification
48-lead LQFP package
ENHANCED FEATURES
Integrated parametric equalizer (EQ)
Stereo microphone with preamplifiers
Integrated PLL for system clocking
Variable sample rate 7 kHz to 96 kHz
7 kHz to 48 kHz in 1 Hz increments
96 kHz for double rate audio
Advanced jack sense with auto topology switching
Software enabled VREFOUT for microphones and external
power amp
Software enabled outputs for jack sharing
Auto down-mix and channel spreading
Microphone to mono output
Stereo microphone analog passthrough to outputs
Built-in stereo microphone and Center/LFE pin sharing
Selectable Center/LFE tip/ring swapping to support various
speaker products
MIC1
MIC2
PHONE_IN
CD_L
CD_GND
CD_R
AUX_L
AUX_R
LINE_IN_L
LINE_IN_R
LFE_OUT
G
G
CD
DIFF AMP
MZ A
CENTER_OUT
MZ A
LINE_OUT_L MZ A
MONO_OUT
MA
LINE_OUT_R MZ A
SURR_OUT_L/
HP_OUT_L
HP M
A
SURR_OUT_R/
HP_OUT_R
HP M A
FUNCTIONAL BLOCK DIAGRAM
AD1985
VREFOUT
VREF
XTL_OUT XTL_IN SPDIF_OUT
ZG
VOLTAGE
REFERENCE
CODEC CORE
PCM L/R
ADC RATE
G
M
16-BIT
Σ-∆ ADC
G
M
16-BIT
Σ-∆ ADC
PLL
ADC
SLOT
LOGIC
SPDIF
TX
ID0
ID1
PCM C/LFE
DAC RATE
M
GA
20-BIT
Σ-∆ DAC
GA GA GA GA GA
M M M GA M GA M GA M GA M M M
M MM M
Σ
Σ
M
G = GAIN
A = ATTENUATION
M = MUTE
Z = HIGH Z
Σ
M
M
GA
20-BIT
Σ-∆ DAC
MA
M GA
M GA
M GA
M GA
PC BEEP
GENERATOR
PCM FRONT
DAC RATE
20-BIT
Σ-∆ DAC
20-BIT
Σ-∆ DAC
20-BIT
Σ-∆ DAC
20-BIT
Σ-∆ DAC
PCM SURR
DAC RATE
DAC
SLOT
LOGIC
EQ
RESET
SYNC
BITCLK
SDATA_OUT
SDATA_IN
EQ AC '97
CONTROL
REGISTERS
ANALOG MIXING
CONTROL
EAPD JACK SENSE
EAPD JS0 JS1 JS2 JS3
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
AD1985
ANALOG MIXER—INPUT GAIN/AMPLIFIERS/ATTENUATORS
Table 5.
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
CD to LINE_OUT
LINE, AUX, PHONE, to LINE_OUT
MIC1 or MIC2 to LINE_OUT
Step Size: All Mixer Inputs, Except PC Beep
Input Gain/Attenuation Range (+12 dB to –34.5 dB): All Mixer Inputs, Except PC Beep
Min Typ Max Unit
90 dB
85 dB
80 dB
1.5 dB
46.5 dB
DIGITAL DECIMATION AND INTERPOLATION FILTERS1
Table 6.
Parameter
PASS BAND
PASS-BAND RIPPLE
TRANSITION BAND
STOP BAND
STOP-BAND REJECTION
GROUP DELAY
GROUP DELAY VARIATION OVER PASS BAND
Min
0
0.4 ×
fS
0.6 ×
fS
–74
Typ
16/fS
0
Max
0.4 × fS
±0.09
0.6 × fS
Unit
Hz
dB
Hz
∞ Hz
dB
s
µs
ANALOG-TO-DIGITAL CONVERTERS
Table 7.
Parameter
RESOLUTION
TOTAL HARMONIC DISTORTION (THD)
DYNAMIC RANGE (–60 dB IN; THD+N REFERENCED TO FULL-SCALE; A-WEIGHTED)
SIGNAL-TO-INTERMODULATION DISTORTION (CCIF METHOD)1
ADC CROSSTALK1
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)
LINE_IN to Other
GAIN ERROR (FULL-SCALE SPAN RELATIVE TO NOMINAL INPUT VOLTAGE)
INTERCHANNEL GAIN MISMATCH (DIFFERENCE OF GAIN ERRORS)
ADC OFFSET ERROR1
Min Typ Max Unit
16 Bits
−85 dB
84 dB
85 dB
−85 dB
−95 dB
±10 %
±0.5 dB
±5 mV
DIGITAL-TO-ANALOG CONVERTERS
Table 8.
Parameter
RESOLUTION
TOTAL HARMONIC DISTORTION (THD); LINE_OUT, C/LFE
TOTAL HARMONIC DISTORTION (THD); HP_OUT
DYNAMIC RANGE (–60 dB IN; THD+N REFERENCED TO FULL-SCALE; A-WEIGHTED)
SIGNAL-TO-INTERMODULATION DISTORTION (CCIF METHOD)1
GAIN ERROR (OUTPUT FULL-SCALE VOLTAGE RELATIVE TO NOMINAL OUTPUT FULL-SCALE VOLTAGE)2
INTERCHANNEL GAIN MISMATCH (DIFFERENCE OF GAIN ERRORS)
DAC CROSSTALK (INPUT L, ZERO R, READ R_OUT; INPUT R, ZERO L, READ L_OUT)1
TOTAL OUT-OF-BAND ENERGY (MEASURED FROM 0.6 × fS TO 100 KHZ)1
Min
Typ
20
–90
–75
90
100
±10
–100
–85
Max
±0.7
Unit
Bits
dB
dB
dB
dB
%
dB
dB
dB
1 Guaranteed, not tested.
2 C/LFE specified with 10 kΩ load.
Rev. A | Page 5 of 48
5 Page 
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD1985
48 47 46 45 44 43 42 41 40 39 38 37
DVDD1 1
XTL_IN 2
XTL_OUT 3
DVSS1 4
SDATA_OUT 5
BIT_CLK 6
DVSS2 7
SDATA_IN 8
DVDD2 9
SYNC 10
RESET 11
JS3 12
PIN 1
IDENTIFIER
AD1985
TOP VIEW
(Not to Scale)
36 LINE_OUT_R (FRONT)/SURR_R
35 LINE_OUT_L (FRONT)/SURR_L
34 AVDD4
33 JS2
32 LFE_OUT
31 CENTER_OUT
30 AFILT2
29 AFILT1
28 VREFOUT
27 VREF
26 AVSS1
25 AVDD1
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
Figure 10. 48-Lead LQFP Pin Configuration
Circuit Layout Note: In normal operation, Surround and Line Out are swapped to provide headphone drive on line outputs. Therefore, Pins 35 and 36 become the
surround L/R outputs and Pins 39 and 41 become the Line Out (Front) L/R outputs with headphone drive. See Bits LOSEL and HPSEL in Register 0x76 for details.
PIN FUNCTION DESCRIPTIONS
Table 17. Digital I/O
Mnemonic Pin No. I/O Description
XTL_IN
2
I Crystal Input (24.576 MHz) or External Clock In (24.576 MHz, 14.31818 MHz, or 48.000 MHz).
XTL_OUT
3
O Crystal Output.
SDATA_OUT 5
I AC Link Serial Data Output. AD1985 input stream.
BIT_CLK
6
O/I AC Link Bit Clock. 12.288 MHz serial data clock. (Input pin, for secondary mode only.)
SDATA_IN 8
O AC Link Serial Data Input. AD1985 output stream.
SYNC
10 I AC Link Frame Sync.
RESET 11 I AC Link Reset. AD1985 master hardware reset.
SPDIF
48 O SPDIF Output.
Table 18. Chip Selects/Clock Strapping
Mnemonic Pin No. I/O Description
ID0 45 I Chip Select Input 0 (Active Low).
This pin can also be used as the chain input from a secondary codec.
ID1 46 I Chip Select Input 1 (Active Low).
Table 19. Jack Sense/EAPD
Mnemonic Pin No. Type
EAPD
47 O
JS0 17 I
JS1 16 I
JS2 33 I
JS3 12 I
Description
EAPD Output.
JACK SENSE 0 Input.
JACK SENSE 1 Input.
JACK SENSE 2 Input.
JACK SENSE 3 Input.
Rev. A | Page 11 of 48
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD1985.PDF ] | |
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