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PDF AD1879 Data sheet ( Hoja de datos )
| Número de pieza | AD1879 | |
| Descripción | High Performance 16-/18-Bit Stereo ADCs | |
| Fabricantes | Analog Devices | |
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a
High Performance
16-/18-Bit ⌺⌬ Stereo ADCs
AD1878/AD1879*
FEATURES
Fully Differential Dual Channel Analog Inputs
103 dB Signal-to-Noise (AD1879 typ)
–98 dB THD+N (AD1879 typ)
0.001 dB Passband Ripple and 115 dB Stopband
Attenuation
Fifth-Order, 64 Times Oversampling ⌺⌬ Modulator
Single Stage, Linear Phase Decimator
256 ؋ FS Input Clock
APPLICATIONS
Digital Tape Recorders
Professional, DCC, and DAT
A/V Digital Amplifiers
CD-R
Sound Reinforcement
PRODUCT OVERVIEW
The AD1879 is a two-channel, 18-bit oversampling ADC based
on ∑∆ technology and intended primarily for digital audio appli-
cations. The AD1878 is identical to the 18-bit AD1879 except
that it outputs 16-bit data words. Statements in this data sheet
should be read as applying to both parts unless otherwise noted.
Each input channel of these ADCs is fully differential. Each
data conversion channel consists of a fifth order one-bit noise
shaping modulator and a digital decimation filter. An on-chip
voltage reference provides a voltage source to both channels sta-
ble over temperature and time. Digital output data from both
channels is time-multiplexed to a single, flexible serial interface.
The AD1878/AD1879 accepts a 256 × FS input master clock.
Input signals are sampled at 64 × FS on switched-capacitors,
eliminating external sample-and-hold amplifiers and minimizing
the requirements for antialias filtering at the input. With simpli-
fied antialiasing, linear phase can be preserved across the passband.
The AD1878/AD1879’s proprietary fifth-order differential
switched-capacitor modulator architecture shapes the one-bit
comparator’s quantization noise out of the audio passband. The
high order of the modulator randomizes the modulator output,
reducing idle tones in the AD1878/AD1879 to very low levels.
The AD1878/AD1879’s differential architecture provides in-
creased dynamic range and excellent common-mode rejection
characteristics. Because its modulator is single-bit, AD1878/
AD1879 is inherently monotonic and has no mechanism for
producing differential linearity errors.
The digital decimation filters are single-stage, 4095-tap finite
impulse response filters for filtering the modulator’s high fre-
quency quantization noise and reducing the 64 × FS single-bit
output data rate to a FS word rate. They provide linear
*Protected by U.S. Patent Numbers 5055843, 5126653, and others pending.
FUNCTIONAL BLOCK DIAGRAM
LRCK 1
BCK 2
S0 3
64/32 4
DVDD 5
DGND 6
NC 7
AVSS1 8
AVSS2 9
AGND 10
APD 11
VINR– 12
VINR+ 13
REFR 14
SERIAL OUTPUT
INTERFACE
DIGITAL
CHIP
SINGLE-STAGE,
4k-TAP
FIR DECIMATION
FILTER
SINGLE-STAGE,
4k-TAP
FIR DECIMATION
FILTER
ANALOG
D D CHIP D D
A AA A
C CC C
VOLTAGE
REFERENCE
28 WCK
27 DATA
26 CLOCK
25 S1
24 RESET
23 DGND
22 DVDD
21 AVSS1
20 AVDD2
19 AVDD1
18 AGND
17 VINL–
16 VINL+
15 REFL
phase and a narrow transition band that permits the digitization
of 20 kHz signals while preventing aliasing into the passband
even when using a 44.1 kHz sampling frequency. Passband
ripple is less the 0.001 dB, and stopband attenuation exceeds
115 dB.
The flexible serial output port produces data in twos-complement,
MSB-first format. Input and output signals are to TTL and
CMOS-compatible logic levels. The port is configured by pin
selections. The AD1878/AD1879 can operate in either master
or slave mode. Each 16-/18-bit output word of a stereo pair can
be formatted within a 32-bit field as either right-justified, I2S-
compatible, or at user-selected positions. The output can also be
truncated to 16-bits by formatting into a 16-bit field.
The AD1878/AD1879 consists of two integrated circuits in a
single ceramic 28-pin DIP package. The modulators and refer-
ence are fabricated in a BiCMOS process; the decimator and
output port, in a 1.0 µm CMOS process. Separating these func-
tions reduces digital crosstalk to the analog circuitry. Analog and
digital supply connections are separated to further isolate the
analog circuitry from the digital supplies.
The AD1878/AD1879 operates from ± 5 V power supplies over
the temperature range of –25°C to +70°C.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD1878/AD1879
DEFINITIONS
Dynamic Range
The ratio of a full-scale output signal to the integrated output
noise in the passband (0 kHz to 20 kHz), expressed in decibels
(dB). Dynamic range is measured with a –60 dB input signal
and is equal to (S/[THD+N]) + 60 dB.
Signal to (Noise + Distortion)
The ratio of the root-mean-square (rms) value of the fundamen-
tal input signal to the rms sum of all spectral components in the
passband, expressed in decibels (dB).
Signal to Total Harmonic Distortion (THD)
The ratio of the rms sum of all harmonically related spectral
components in the passband to the fundamental input signal,
expressed either as a percentage (%) or in decibels (dB).
Passband
The region of the frequency spectrum unaffected by the attenu-
ation of the digital decimator’s filter.
Passband Ripple
The peak-to-peak variation in amplitude response from equal
amplitude input signal frequencies within the passband, ex-
pressed in decibels.
Stopband
The region of the frequency spectrum attenuated by the digi-
tal decimator’s filter to the degree specified by “stopband
attenuation.”
Gain Error
With a near full-scale input, the ratio of actual output to ex-
pected output, expressed as a percentage.
Interchannel Gain Mismatch
With near full-scale inputs, the ratio of outputs of the two stereo
channels, expressed in decibels.
Gain Drift
Change in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per °C.
Midscale Offset Error
Output response to a midscale input (i.e., zero volts dc), ex-
pressed in least-significant bits (LSBs).
Midscale Drift
Change in midscale offset error with a change in temperature,
expressed as parts-per-million (ppm) of full scale per °C.
Crosstalk
Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine-wave input on the other channel, expressed
in decibels.
Interchannel Phase Deviation
Difference in input sampling times between stereo channels, ex-
pressed as a phase difference in degrees between 1 kHz inputs.
Power Supply Rejection
With analog inputs grounded, energy at the output when a
300 mV p-p signal is applied to power supply pins, expressed in
decibels of full scale.
Group Delay
Intuitively, the time interval required for an input pulse to ap-
pear at the converter’s output, expressed in milliseconds (ms).
More precisely, the derivative of radian phase with respect to
radian frequency at a given frequency.
Group Delay Variation
The difference in group delays at different input frequencies.
Specified as the difference between largest and the smallest
group delays in the passband, expressed in microseconds (µs).
AD1878/AD1879 PIN LIST
Pin Input/Output Pin Name Description
11 I/O
12 I/O
13 I
14 I
15 I
16 I
17
18 I
19 I
10 I
11 I
12 I
13 I
14 I/O
15 I/O
16 I
17 I
18 I
19 I
20 I
21 I
22 I
23 I
24 I
25 I
26 I
27 O
28 I/O
LRCK
BCK
S0
64/32
DVDD
DGND
N/C
AVSS1
AVSS2
AGND
APD
VINR–
VINR+
REFR
REFL
VINL+
VINL–
AGND
AVDD1
AVDD2
AVSS1
DVDD
DGND
RESET
S1
CLOCK
DATA
WCK
Left/Right Clock
Bit Clock
Mode Select 0
Bit Rate Select
+5 V Digital Supply
Digital Ground
No Connection; Do Not Connect
–5 V Analog Supply
–5 V Analog Logic Supply
Analog Ground
Analog Power Down
Right Inverting Input
Right Noninverting Input
Right Reference Capacitor
Left Reference Capacitor
Left Noninverting Input
Left Inverting Input
Analog Ground
+5 V Analog Supply
+5 V Analog Logic Supply
–5 V Analog Supply
+5 V Digital Supply
Digital Ground
Reset
Mode Select 1
Master Clock Input
Serial Data Output
Word Clock
THEORY OF OPERATION
∑∆ Modulator Noise-Shaping
The stereo, differential analog modulators of the AD1878/
AD1879 employ a proprietary feedforward and feedback archi-
tecture that passes input signals in the audio band with a unity
transfer function yet simultaneously shape the quantization
noise generated by the one-bit comparator out of the audio
band. See Figure 1. Without the ∑∆ architecture, this quantiza-
tion noise would be spread uniformly from dc to one-half the
oversampling frequency, 64 × FS. (Regardless of architecture,
64 times oversampling by itself significantly reduces the quanti-
zation noise in the audio band if the input is properly dithered.
However, the noise reduction is only [log2 64] × 3 dB = 18 dB.)
PIN 1
2
8
1
0.250
(6.35)
MAX
0.200 (5.05)
0.125 (3.18)
0.022 (0.558)
0.014 (0.356)
15
14
0.580 (14.73)
0.485 (12.32)
1.565 (39.70)
1.380 (35.10)
0.060 (1.52)
0.015 (0.38)
0.100
(2.54)
BSC
0.625 (15.87)
0.600 (15.24)
0.015 (0.381)
0.008 (0.204)
0.070 (1.77)
MAX
0.150
(3.81)
MIN
SEATING
PLANE
0.195 (4.95)
0.125 (3.18)
Figure 1. AD1878/AD1879 Modulator Noise-Shaper (One
Channel)
REV. 0
–5–
5 Page 
AD1878/AD1879
32 1 2 3
BCK I/O
14 15 16 17 18 19 20
31 32 1 2 3
14 15 16 17 18 19 20
31 32 1
WCK INPUT
LRCK I/O
PREVIOUS DATA
AD1878 LSB
DATA OUTPUT
ZEROS
LEFT DATA
MSB MSB–1 MSB–2 MSB–3
LSB–1 LSB
ZEROS
RIGHT DATA
MSB MSB–1 MSB–2 MSB–3
LSB–1 LSB
Figure 10. AD1878 64-Bit Frame Output Timing with WCK as Input: WCK Held LO Until 16th BCK
(Master Mode or Slave Mode)
BCK I/O
32 1 2
3
WCK INPUT
14 15 16 17 18 19 20
31 32 1 2 3
14 15 16 17 18 19 20
31 32 1
LRCK I/O
PREVIOUS DATA
AD1879
DATA OUTPUT
LSB
ZEROS
LEFT DATA
MSB MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
LSB–1 LSB
ZEROS
RIGHT DATA
MSB MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
LSB–1 LSB
Figure 11. AD1879 64-Bit Frame Output Timing with WCK as Input: WCK Held LO Until 14th BCK
(Master Mode or Slave Mode)
32 1 2 3
BCK I/O
WCK INPUT
16 17 18 19 20 21 22
LRCK I/O
31 32 1 2 3
16 17 18 19 20 21 22
31 32 1
AD1879
DATA OUTPUT
AD1878
DATA OUTPUT
LEFT DATA
ZEROS MSB MSB–1 LSB–3 LSB-2 LSB–1 LSB
LEFT DATA
ZEROS MSB MSB–1 LSB–1 LSB
ZEROS
ZEROS
RIGHT DATA
ZEROS MSB MSB–1 LSB–3 LSB-2 LSB–1 LSB
RIGHT DATA
ZEROS MSB MSB–1 LSB–1 LSB
ZEROS
ZEROS
Figure 12. AD1878/AD1879 64-Bit Output Frame Timing with WCK as Input: WCK Hl During 1st BCK
(Master Mode or Slave Mode)
16 1 2 3 4 5 6
BCK I/O
15 16 1 2 3 4 5 6
15 16 1
LRCK I/O
AD1879
DATA OUTPUT
AD1878
DATA OUTPUT
LEFT DATA
MSB MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
LEFT DATA
MSB MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
RIGHT DATA
LSB–3 LSB–2 MSB MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
RIGHT DATA
LSB-1 LSB MSB MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
LSB–3 LSB–2
LSB-1 LSB
Figure 13. AD1878/AD1879 32-Bit Output Frame Timing (Master Mode or Slave Mode)
At the other limit, if the word clock (WCK) is HI during the first
bit clock (BCK) of the field, then the MSB of the output word
will be valid on the rising edge of the 2nd bit clock (BCK) as
shown in Figure 12. The effect is to delay the MSB for one bit
clock cycle into the field, making the output data compatible at
the data format level with the I2S data format.
In 64-bit frame modes with word clock (WCK) as an input, the
relative placement of the word clock (WCK) input can vary
from 32-bit field to 32-bit field, even within the same 64-bit
frame. For example, within a single 64-bit frame the left word
could be right-justified (by keeping WCK LO) and the right
word could be in an I2S-compatible data format (by having
WCK HI at the beginning of the second field).
REV. 0
–11–
11 Page | ||
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| PDF Descargar | [ Datasheet AD1879.PDF ] | |
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