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PDF AD1877 Data sheet ( Hoja de datos )
| Número de pieza | AD1877 | |
| Descripción | Single-Supply 16-Bit Stereo ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Single-Supply
16-Bit ⌺⌬ Stereo ADC
AD1877*
FEATURES
Single 5 V Power Supply
Single-Ended Dual-Channel Analog Inputs
92 dB (Typ) Dynamic Range
90 dB (Typ) S/(THD+N)
0.006 dB Decimator Passband Ripple
Fourth-Order, 64-Times Oversampling ⌺⌬ Modulator
Three-Stage, Linear-Phase Decimator
256 ؋ FS or 384 ؋ FS Input Clock
Less than 100 W (Typ) Power-Down Mode
Input Overrange Indication
On-Chip Voltage Reference
Flexible Serial Output Interface
28-Lead SOIC Package
APPLICATIONS
Consumer Digital Audio Receivers
Digital Audio Recorders, Including Portables
CD-R, DCC, MD and DAT
Multimedia and Consumer Electronic Equipment
Sampling Music Synthesizers
Digital Karaoke Systems
PRODUCT OVERVIEW
The AD1877 is a stereo, 16-bit oversampling ADC based on
Sigma Delta (∑∆) technology intended primarily for digital
audio bandwidth applications requiring a single 5 V power supply.
Each single-ended channel consists of a fourth-order one-bit
noise shaping modulator and a digital decimation filter. An on-
chip voltage reference, stable over temperature and time, defines
the full-scale range for both channels. Digital output data from
both channels are time-multiplexed to a single, flexible serial
interface. The AD1877 accepts a 256 × FS or a 384 × FS input
clock (FS is the sampling frequency) and operates in both serial
port “master” and “slave” modes. In slave mode, all clocks must
be externally derived from a common source.
Input signals are sampled at 64 × FS onto internally buffered
switched-capacitors, eliminating external sample-and-hold ampli-
fiers and minimizing the requirements for antialias filtering at the
input. With simplified antialiasing, linear phase can be preserved
across the passband. The on-chip single-ended to differential signal
converters save the board designer from having to provide them
externally. The AD1877’s internal differential architecture provides
increased dynamic range and excellent power supply rejection
characteristics. The AD1877’s proprietary fourth-order differen-
tial switched-capacitor ∑∆ modulator architecture shapes the
*Protected by U.S. Patent Numbers 5055843, 5126653, and others pending.
FUNCTIONAL BLOCK DIAGRAM
LRCK 1
WCLK 2
BCLK 3
DVDD1 4
DGND1 5
RDEDGE 6
S/M 7
384/256 8
AVDD 9
VINL 10
CAPL1 11
CAPL2 12
AGNDL 13
VREFL 14
SERIAL OUTPUT
INTERFACE
CLOCK
DIVIDER
THREE-STAGE FIR
DECIMATION
FILTER
THREE-STAGE FIR
DECIMATION
FILTER
D DD D
A AA A
C CC C
SINGLE TO
SINGLE TO
DIFFERENTIAL INPUT DIFFERENTIAL INPUT
CONVERTER
CONVERTER
VOLTAGE
REFERENCE
AD1877
28 CLKIN
27 TAG
26 SOUT
25 DVDD2
24 DGND2
23 RESET
22 MSBDLY
21 RLJUST
20 AGND
19 VINR
18 CAPR1
17 CAPR2
16 AGNDR
15 VREFR
one-bit comparator’s quantization noise out of the audio pass-
band. The high order of the modulator randomizes the modulator
output, reducing idle tones in the AD1877 to very low levels.
Because its modulator is single-bit, AD1877 is inherently
monotonic and has no mechanism for producing differential
linearity errors.
The input section of the AD1877 uses autocalibration to correct
any dc offset voltage present in the circuit, provided that the inputs
are ac coupled. The single-ended dc input voltage can swing
between 0.7 V and 3.8 V typically. The AD1877 antialias input
circuit requires four external 470 pF NPO ceramic chip filter
capacitors, two for each channel. No active electronics are
needed. Decoupling capacitors for the supply and reference pins
are also required.
The dual digital decimation filters are triple-stage, finite impulse
response filters for effectively removing the modulator’s high
frequency quantization noise and reducing the 64 × FS single-bit
output data rate to an FS word rate. They provide linear phase
and a narrow transition band that properly digitizes 20 kHz signals
at a 44.1 kHz sampling frequency. Passband ripple is less than
0.006 dB, and stopband attenuation exceeds 90 dB.
(Continued on Page 6)
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
AD1877
PIN FUNCTION DESCRIPTIONS
Input/ Pin
Pin Output Name
Description
1 I/O
LRCK
Left/Right Clock
2 I/O
WCLK Word Clock
3 I/O
BCLK Bit Clock
4I
5I
DVDD1 5 V Digital Supply
DGND1 Digital Ground
6I
7I
8I
RDEDGE Read Edge Polarity Select
S/M Slave/Master Select
384/256 Clock Mode
9I
10 I
11 O
AVDD
VINL
CAPL1
5 V Analog Supply
Left Channel Input
Left External Filter Capacitor 1
12 O
CAPL2 Left External Filter Capacitor 2
13 I
AGNDL Left Analog Ground
14 O
15 O
16 I
VREFL
VREFR
AGNDR
Left Reference Voltage Output
Right Reference Voltage Output
Right Analog Ground
17 O
18 O
CAPR2
CAPR1
Right External Filter Capacitor 2
Right External Filter Capacitor 1
19 I
20 I
21 I
22 I
23 I
VINR
AGND
RLJUST
MSBDLY
RESET
Right Channel Input
Analog Ground
Right/Left Justify
Delay MSB One BCLK Period
Reset
24 I
DGND2 Digital Ground
25 I
26 O
DVDD2
SOUT
5 V Digital Supply
Serial Data Output
27 O
TAG
Serial Overrange Output
28 I
CLKIN Master Clock
DEFINITIONS
Dynamic Range
The ratio of a full-scale output signal to the integrated output
noise in the passband (20 Hz to 20 kHz), expressed in decibels
(dB). Dynamic range is measured with a –60 dB input signal
and is equal to (S/[THD+N]) 60 dB. Note that spurious har-
monics are below the noise with a –60 dB input, so the noise
level establishes the dynamic range. The dynamic range is speci-
fied with and without an A-Weight filter applied.
Signal to (Total Harmonic Distortion + Noise)
(S/(THD + N))
The ratio of the root-mean-square (rms) value of the fundamen-
tal input signal to the rms sum of all other spectral components
in the passband, expressed in decibels (dB).
Signal to Total Harmonic Distortion (S/THD)
The ratio of the rms value of the fundamental input signal to the
rms sum of all harmonically related spectral components in the
passband, expressed in decibels.
Passband
The region of the frequency spectrum unaffected by the attenu-
ation of the digital decimator’s filter.
Passband Ripple
The peak-to-peak variation in amplitude response from equal-
amplitude input signal frequencies within the passband,
expressed in decibels.
Stopband
The region of the frequency spectrum attenuated by the digital
decimator’s filter to the degree specified by “stopband
attenuation.”
Gain Error
With a near full-scale input, the ratio of actual output to
expected output, expressed as a percentage.
Interchannel Gain Mismatch
With identical near full-scale inputs, the ratio of outputs of the
two stereo channels, expressed in decibels.
Gain Drift
Change in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per °C.
Midscale Offset Error
Output response to a midscale dc input, expressed in least-
significant bits (LSBs).
Midscale Drift
Change in midscale offset error with a change in temperature,
expressed as parts-per-million (ppm) per °C.
Crosstalk (EIAJ Method)
Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine-wave input on the other channel, expressed
in decibels.
Power Supply Rejection
With no analog input, signal present at the output when a
300 mV p-p signal is applied to power supply pins, expressed in
decibels of full scale.
Group Delay
Intuitively, the time interval required for an input pulse to
appear at the converter’s output, expressed in milliseconds
(ms). More precisely, the derivative of radian phase with respect
to radian frequency at a given frequency.
Group Delay Variation
The difference in group delays at different input frequencies.
Specified as the difference between largest and the smallest
group delays in the passband, expressed in microseconds (µs).
REV. A
–5–
5 Page 
AD1877
Two modes deserve special discussion. The first special mode,
“Slave Mode, Data Position Controlled by WCLK Input” (S/M
= HI, RLJUST = HI, MSBDLY = LO), shown in Figure 8, is
the only mode in which WCLK is an input. The 16-bit output
data words can be placed at user-defined locations within 32-bit
fields. The MSB will appear in the BCLK period after WCLK is
detected HI by the BCLK sampling edge. If WCLK is HI dur-
ing the first BCLK of the 32-bit field (if WCLK is tied HI for
example), then the MSB of the output word will be valid on the
sampling edge of the second BCLK. The effect is to delay the
MSB for one bit clock cycle into the field, making the output
data compatible at the data format level with the I2S data for-
mat. Note that the relative placement of the WCLK input can
vary from 32-bit field to 32-bit field, even within the same
64-bit frame. For example, within a single 64-bit frame, the left
word could be right justified (by pulsing WCLK HI on the 16th
BCLK) and the right word could be in an I2S-compatible data
format (by having WCLK HI at the beginning of the second field).
In the second special mode “Master Mode, Right-Justified with
MSB Delay, WCLK Pulsed in 17th Cycle” (S/M = LO,
RLJUST = HI, MSBDLY = LO), shown in Figure 12, WCLK
is an output and is pulsed for one cycle by the AD1877. The
MSB is valid on the 18th BCLK sampling edge, and the LSB
extends into the first BCLK period of the next 32-bit field.
Timing Parameters
For master modes, a BCLK transmitting edge (labeled “XMIT”)
will be delayed from a CLKIN rising edge by tDLYCKB, as shown
in Figure 17. A LRCK transition will be delayed from a BCLK
transmitting edge by tDLYBLR. A WCLK rising edge will be
delayed from a BCLK transmitting edge by tDLYBWR, and a WCLK
falling edge will be delayed from a BCLK transmitting edge by
tDLYBWF. The DATA and TAG outputs will be delayed from a
transmitting edge of BCLK by tDLYDT.
For slave modes, an LRCK transition must be setup to a BCLK
sampling edge (labeled “SAMPLE”) by tSETLRBS. The DATA
and TAG outputs will be delayed from an LRCK transition by
tDLYLRDT, and DATA and TAG outputs will be delayed from
BCLK transmitting edge by tDLYBDT. For “Slave Mode, Data
Position Controlled by WCLK Input,” WCLK must be setup to
a BCLK sampling edge by tSETWBS.
For both master and slave modes, BCLK must have a minimum
LO pulsewidth of tBPWL, and a minimum HI pulsewidth of tBPWH.
The AD1877 CLKIN and RESET timing is shown in Figure
19. CLKIN must have a minimum LO pulsewidth of tCPWL, and
a minimum HI pulse width of tCPWH. The minimum period of
CLKIN is given by tCLKIN. RESET must have a minimum LO
pulsewidth of tRPWL. Note that there are no setup or hold time
requirements for RESET.
Synchronizing Multiple AD1877s
Multiple AD1877s can be synchronized by making all the
AD1877s serial port slaves. This option is illustrated in
Figure 6. See the “Reset, Autocalibration and Power Down”
section above for additional information.
CLOCK
SOURCE
#1 AD1877
SLAVE MODE
RESET
CLKIN
DATA
BCLK
WCLK
LRCK
#2 AD1877
SLAVE MODE
RESET
CLKIN
DATA
BCLK
WCLK
LRCK
#N AD1877
SLAVE MODE
RESET
CLKIN
DATA
BCLK
WCLK
LRCK
Figure 6. Synchronizing Multiple AD1877s
REV. A
–11–
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet AD1877.PDF ] | |
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