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PDF AD1853 Data sheet ( Hoja de datos )
| Número de pieza | AD1853 | |
| Descripción | Stereo/ 24-Bit/ 192 kHz/ Multibit DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD1853 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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a Stereo, 24-Bit, 192 kHz, Multibit ⌺⌬ DAC
AD1853*
FEATURES
5 V Stereo Audio DAC System
Accepts 16-/18-/20-/24-Bit Data
Supports 24 Bits and 192 kHz Sample Rate
Accepts a Wide Range of Sample Rates Including:
32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz and 192 kHz
Multibit Sigma-Delta Modulator with “Perfect Differential
Linearity Restoration” for Reduced Idle Tones and
Noise Floor
Data Directed Scrambling DAC—Least Sensitive to Jitter
Differential Output for Optimum Performance
120 dB Signal to Noise (Not Muted) at 48 kHz
(A-Weighted Mono)
117 dB Signal to Noise (Not Muted) at 48 kHz
(A-Weighted Stereo)
119 dB Dynamic Range (Not Muted) at 48 kHz Sample
Rate (A-Weighted Mono)
116 dB Dynamic Range (Not Muted) at 48 kHz Sample
Rate (A-Weighted Stereo)
–107 dB THD+N (Mono Application Circuit, See Figure 30)
–104 dB THD+N (Stereo)
115 dB Stopband Attenuation (96 kHz)
On-Chip Clickless Volume Control
Hardware and Software Controllable Clickless Mute
Serial (SPI) Control for: Serial Mode, Number of Bits,
Interpolation Factor, Volume, Mute, De-Emphasis, Reset
Digital De-Emphasis Processing for 32, 44.1 and 48 kHz
Sample Rates
Clock Auto-Divide Circuit Supports Five Master-Clock
Frequencies
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S-Compatible and DSP Serial Port Modes
28-Lead SSOP Plastic Package
APPLICATIONS
Hi End: DVD, CD, Home Theater Systems, Automotive
Audio Systems, Sampling Musical Keyboards, Digital
Mixing Consoles, Digital Audio Effects Processors
PRODUCT OVERVIEW
The AD1853 is a complete high performance single-chip stereo
digital audio playback system. It is comprised of a high per-
formance digital interpolation filter, a multibit sigma-delta
modulator, and a continuous-time current-out analog DAC
section. Other features include an on-chip clickless stereo at-
tenuator and mute capability, programmed through an SPI-
compatible serial control port. The AD1853 is fully compatible
with all known DVD formats and supports 48 kHz, 96 kHz and
192 kHz sample rates with up to 24 bits word lengths. It also
provides the “Redbook” standard 50 µs/15 µs digital de-emphasis
filters at sample rates of 32 kHz, 44.1 kHz and 48 kHz.
The AD1853 has a very flexible serial data input port that
allows for glueless interconnection to a variety of ADCs, DSP
chips, AES/EBU receivers and sample rate converters. The
AD1853 can be configured in left-justified, I2S, right-justified,
or DSP serial port compatible modes. The AD1853 accepts
serial audio data in MSB first, twos complement format.
The AD1853 operates from a single +5 V power supply. It is
fabricated on a single monolithic integrated circuit and is housed in
a 28-lead SSOP package for operation over the temperature
range 0°C to +70°C.
FUNCTIONAL BLOCK DIAGRAM
INT2؋ INT4؋
CONTROL DATA
VOLUME INPUT
MUTE
3
DIGITAL
SUPPLY
2
CLOCK
IN
AD1853
SERIAL CONTROL
INTERFACE
VOLTAGE
REFERENCE
AUTO-CLOCK
DIVIDE CIRCUIT
DIGITAL
DATA INPUT
SERIAL 2
MODE
SERIAL
DATA
INTERFACE
ATTEN/
MUTE
ATTEN/
MUTE
8 ؋ FS
INTERPOLATOR
8 ؋ FS
INTERPOLATOR
MULTIBIT SIGMA-
DELTA MODULATOR
MULTIBIT SIGMA-
DELTA MODULATOR
IDAC
IDAC
ANALOG
OUTPUTS
*Patents Pending.
RESET
MUTE
DE-EMPHASIS
2
ANALOG
SUPPLY
2
ZERO
FLAG
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1 page  
AD1853
PIN FUNCTION DESCRIPTIONS
Pin Input/Output Pin Name Description
1I
2I
3I
4I
5I
6I
7I
8O
9I
10 I
11 I
12 O
13 O
14 O
15 I
16 O
17 O
18 I
19 O
20 I
21 I
22 O
23 I
24 I
25 I
26 I
27 I
28 I
DGND
MCLK
CLATCH
CCLK
CDATA
INT4×
INT2×
ZEROR
DEEMP
IREF
AGND
OUTL+
OUTL–
FILTR
FCR
OUTR–
OUTR+
AVDD
FILTB
IDPM1
IDPM0
ZEROL
MUTE
RST
L/RCLK
BCLK
SDATA
DVDD
Digital Ground.
Master Clock Input. Connect to an external clock source. See Table II for allowable
frequencies.
Latch input for control data. This input is rising-edge sensitive.
Control clock input for control data. Control input data must be valid on the rising edge
of CCLK. CCLK may be continuous or gated.
Serial control input, MSB first, containing 16 bits of unsigned data. Used for specifying
control information and channel-specific attenuation.
Assert HI to select interpolation ratio of 4×, for use with double-speed inputs (88 kHz or
96 kHz). Assert LO to select 8× interpolation ratio.
Assert HI to select interpolation ratio of 2×, for quad-speed inputs (176 kHz or 192 kHz).
Assert LO to select 8× interpolation ratio.
Right Channel Zero Flag Output. This pin goes HI when Right Channel has no signal
input for more than 1024 LR Clock Cycles.
De-Emphasis. Digital de-emphasis is enabled when this input signal is HI. This is used to
impose a 50 µs/15 µs response characteristic on the output audio spectrum at an assumed
44.1 kHz sample rate. Curves for 32 kHz and 48 kHz sample rates may be selected via
SPI control register.
Connection point for external bias resistor. Voltage held at VREF.
Analog Ground.
Left Channel Positive line level analog output.
Left Channel Negative line level analog output.
Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage refer-
ence with parallel 10 µF and 0.1 µF capacitors to the AGND (Pin 11).
Filter cap return pin for cap connected to FILTB (Pin 19).
Right Channel Negative line level analog output.
Right Channel Positive line level analog output.
Analog Power Supply. Connect to analog +5 V supply.
Filter Capacitor connection, connect 10 µF capacitor to FCR (Pin 15).
Input serial data port mode control one. With IDPM0, defines one of four serial modes.
Input serial data port mode control zero. With IDPM1, defines one of four serial modes.
Left Channel Zero Flag output. This pin goes HI when Left Channel has no signal input
for more than 1024 LR Clock Cycles.
Mute. Assert HI to mute both stereo analog outputs. Deassert LO for normal operation.
Reset. The AD1853 is placed in a reset state when this pin is held LO. The AD1853 is
reset on the rising edge of this signal. The serial control port registers are reset to the
default values. Connect HI for normal operation.
Left/Right clock input for input data. Must run continuously.
Bit clock input for input data.
Serial input, MSB first, containing two channels of 16/18/20/24 bit twos-complement
data.
Digital Power Supply Connect to digital +5 V supply.
REV. A
–5–
5 Page 
Typical Performance Characteristics–AD1853
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–10 5
10 15 20 25 30 35 40
FREQUENCY – kHz
Figure 11. 44 kHz Passband Response 4× Mode, 96 kHz
Sample Rate
0
–20
–40
–60
–80
–100
–120
–140
–160
0
50 100 150 200 250 300
FREQUENCY – kHz
Figure 14. Complete Response, 4× Mode, 96 kHz
Sample Rate
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
10 20 30 40 50 60 70 80
FREQUENCY – kHz
Figure 12. 88 kHz Passband Response 2× Mode, 192 kHz
Sample Rate
–50
–60
–70
–80
–90
–100
–110
–120
10
100 1k
FREQUENCY – Hz
10k
Figure 13. THD vs. Frequency Input @ –3 dBFS, SR 48 kHz
0
–20
–40
–60
–80
–100
–120
–140
–160
0
50 100 150 200 250
FREQUENCY – kHz
Figure 15. Complete Response, 2× Mode, 192 kHz
Sample Rate
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–100
–80 –60 –40
dBFS
–20
0
Figure 16. THD + N Ratio vs. Amplitude Input 1 kHz,
SR 48 kHz, 24-Bit
REV. A
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD1853.PDF ] | |
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