PDF AD1849 Data sheet ( Hoja de datos )

Número de pieza	AD1849
Descripción	Parallel-Port 16-Bit SoundPort Stereo Codec
Fabricantes	Analog Devices
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No Preview Available ! a Parallel-Port 16-Bit SoundPort Stereo Codec AD1848K FEATURES Single-Chip Integrated ∑∆ Digital Audio Stereo Codec Supports the Microsoft Windows Sound System® Multiple Channels of Stereo Input Analog and Digital Signal Mixing Programmable Gain and Attenuation On-Chip Signal Filters Digital Interpolation Analog Output Low-Pass Sample Rates from 5.5 kHz to 48 kHz 68-Lead PLCC and 68-Lead TQFP Packages Operation from +5 V Supplies Byte-Wide Parallel Interface to ISA and EISA Buses Supports One or Two DMA Channels and Programmed I/O PRODUCT OVERVIEW The Parallel-Port AD1848K SoundPort® Stereo Codec inte- grates the key audio data conversion and control functions into a single integrated circuit. The AD1848K is intended to provide a complete, single-chip audio solution for business audio and multimedia applications requiring operation from a single +5 V SoundPort is a registered trademark of Analog Devices, Inc. supply. It provides a direct, byte-wide interface to both ISA (“AT”) and EISA computer buses for simplified implementa- tion on a computer motherboard or add-in card. The AD1848K generates enable and direction controls for IC buffers such as 74_245. The AD1848K SoundPort Stereo Codec supports a DMA re- quest/grant architecture for transferring data with the host com- puter bus. One or two DMA channels can be supported. Programmed I/O (PIO) mode is also supported for control register accesses and for applications lacking DMA control. Two input control lines support mixed direct and indirect addressing of twenty-one internal control registers over this asynchronous interface. External circuit requirements are limited to a minimal number of low cost support components. Anti-imaging DAC output fil- ters are incorporated on-chip. Dynamic range exceeds 80 dB over the 20 kHz audio band. Sample rates from 5.5 kHz to 48 kHz are supported from external crystals. The Codec includes a stereo pair of ∑∆ analog-to-digital converters and a stereo pair of ∑∆ digital-to-analog converters. Inputs to the ADC can be selected from four stereo pairs of (Continued on page 9) FUNCTIONAL BLOCK DIAGRAM ANALOG ANALOG SUPPLY DIGITAL SUPPLY CRYSTALS 22 POWER DOWN DIGITAL L_LINE R_LINE L_MIC R_MIC L_AUX1 R_AUX1 L_OUT R_OUT L_AUX2 R_AUX2 L GAIN 20 dB MUX R GAIN ∑∆ A/D CONVERTER ∑∆ A/D CONVERTER OSCILLATORS 16 µ/ A L 16 A W GAIN/ATTEN/MUTE L ∑ ATTEN/ MUTE R ∑ ATTEN/ MUTE ANALOG FILTER ANALOG FILTER ∑∆ D/A CONVERTER ∑∆ D/A CONVERTER DIGITAL MIX INTERPOL ATTENUATE ∑ INTERPOL ATTENUATE ∑ µ/ A L A W P A R A L L E L P O R T 2 8 2 GAIN/ATTEN/MUTE REFERENCE CONTROL REGS 2 PLAYBACK REQ PLAYBACK ACK CAPTURE REQ CAPTURE ACK ADR1:0 DATA7:0 CS WR RD BUS DRIVER CONTROL HOST DMA INTERRUPT EXTERNAL CONTROL 2.25V REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 1 page AD1848K TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE AND V DD = VCC = 5.0 V ؎5%) Min Max Units WR/RD Strobe Width (tSTW) WR/RD Rising to WR/RD Falling (tBWND) Write Data Setup to WR Rising (tWDSU) RD Falling to Valid Read Data (tRDDV) CS Setup to WR/RD Falling (tCSSU) CS Hold from WR/RD Rising (tCSHD) Adr Setup to WR/RD Falling (tADSU) Adr Hold from WR/RD Rising (tADHD) DAK Rising to WR/RD Falling (tSUDK1) DAK Falling to WR/RD Rising (tSUDK2) DAK Setup to WR/RD Falling (tDKSU) Data Hold from RD Rising (tDHD1) Data Hold from WR Rising (tDHD2) DRQ Hold from WR/RD Falling (tDRHD) DAK Hold from WR Rising (tDKHDa) DAK Hold from RD Rising (tDKHDb) DBEN/DBDIR delay from WR/RD Falling (tDBDL) 110 110 22 30 70 10 0 10 10 60 0 25 0 20 15 0 25 50 50 0 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns POWER SUPPLY Power Supply Range – Analog Power Supply Range – 5 V Digital Power Supply Current – 5 V Operating (5 V Supplies, 10 kΩ Load) Analog Supply Current – 5 V Operating (10 kΩ Load) Digital Supply Current – 5 V Operating (10 kΩ Load) Digital Power Supply Current – Power Down Analog Power Supply Current – Power Down Power Dissipation – 5 V Operating (Current • Nominal Supplies) Power Dissipation – Power Down (Current • Nominal Supplies) Power Supply Rejection (100 mV p-p Signal @ 1 kHz)* (At Both Analog and Digital Supply Pins, Both ADCs and DACs) Min Max 4.75 5.25 4.75 5.25 120 65 55 1 1 600 10 40 Units V V mA mA mA mA mA mW mW dB FS CLOCK SPECIFICATIONS* Input Clock Frequency Recommended Clock Duty Cycle Tolerance Initialization Time 16.9344 MHz Crystal Selected 24.576 MHz Crystal Selected *Guaranteed, not tested Specifications subject to change without notice. Min Max 27 ± 10 70 90 Units MHz % ms ms REV. 0 –5– 5 Page AD1848K CONTROL REGISTERS Control Register Architecture The AD1848K SoundPort Stereo Codec accepts both data and control information through its byte-wide parallel port. Indirect addressing minimizes the number of external pins required to access all 21 of its byte-wide internal registers. Only two external address pins, ADR1:0, are required to accomplish all data and control transfers. These pins select one of five direct registers. (ADR1:0 = 3 addresses two registers, depending on whether the transfer is a playback or a capture.) ADR1:0 Register Name 0 Index Address Register 1 Indexed Data Register 2 Status Register 3 PIO Data Registers Figure 4. AD1848K Direct Register Map A write to or a read from the Indexed Data Register will access the indirect register which is indexed by the value most recently written to the Index Address Register. The Status Register and the PIO Data Register are always accessible directly, without in- dexing. The 16 indirect registers are indexed in Figure 5. Index Register Name 0 Left Input Control 1 Right Input Control 2 Left Aux #1 Input Control 3 Right Aux #1 Input Control 4 Left Aux #2 Input Control 5 Right Aux #2 Input Control 6 Left Output Control 7 Right Output Control 8 Clock and Data Format 9 Interface Configuration 10 Pin Control 11 Test and Initialization 12 Miscellaneous Information 13 Digital Mix 14 Upper Base Count 15 Lower Base Count Figure 5. AD1848K Indirect Register Map A detailed map of all direct and indirect register contents is summarized for reference as follows: Direct Registers: ADR1:0 0 1 2 3 3 Data 7 INIT IXD7 CU/L CD7 PD7 Data 6 MCE IXD6 CL/R CD6 PD6 Data 5 TRD IXD5 CRDY CD5 PD5 Data 4 res IXD4 SOUR CD4 PD4 Data 3 IXA3 IXD3 PU/L CD3 PD3 Data 2 IXA2 IXD2 PL/R CD2 PD2 Data 1 IXA1 IXD1 PRDY CD1 PD1 Data 0 IXA0 IXD0 INT CD0 PD0 Indirect Registers: IXA3:0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Data 7 LSS1 RSS1 LMX1 RMX1 LMX2 RMX2 LDM RDM res CPIO XCTL1 COR res DMA5 UB7 LB7 Data 6 LSS0 RSS0 res res res res res res FMT PPIO XCTL0 PUR res DMA4 UB6 LB6 Data 5 LMGE RMGE res res res res LDA5 RDA5 L/C res res ACI res DMA3 UB5 LB5 Data 4 res res LX1A4 RX1A4 LX2A4 RX2A4 LDA4 RDA4 S/M res res DRS res DMA2 UB4 LB4 Data 3 LIG3 RIG3 LX1A3 RX1A3 LX2A3 RX2A3 LDA3 RDA3 CFS2 ACAL res ORR1 ID3 DMA1 UB3 LB3 Data 2 LIG2 RIG2 LX1A2 RX1A2 LX2A2 RX2A2 LDA2 RDA2 CFS1 SDC res ORR0 ID2 DMA0 UB2 LB2 Data 1 LIG1 RIG1 LX1A1 RX1A1 LX2A1 RX2A1 LDA1 RDA1 CFS0 CEN IEN ORL1 ID1 res UB1 LB1 Data 0 LIG0 RIG0 LX1A0 RX1A0 LX2A0 RX2A0 LDA0 RDA0 CSS PEN res ORL0 ID0 DME UB0 LB0 Figure 6. AD1848K Register Summary Note that the only sticky bit in any of the AD1848K control registers is the interrupt (INT) bit. All other bits change with every sample period. REV. 0 –11– 11 Page

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