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PDF AD1847 Data sheet ( Hoja de datos )
| Número de pieza | AD1847 | |
| Descripción | Serial-Port 16-Bit SoundPort Stereo Codec | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Serial-Port 16-Bit
SoundPort Stereo Codec
AD1847
FEATURES
Single-Chip Integrated ⌺⌬ Digital Audio Stereo Codec
Supports the Microsoft Windows Sound System*
Multiple Channels of Stereo Input
Analog and Digital Signal Mixing
Programmable Gain and Attenuation
On-Chip Signal Filters
Digital Interpolation and Decimation
Analog Output Low-Pass
Sample Rates from 5.5 kHz to 48 kHz
44-Lead PLCC and TQFP Packages
Operation from +5 V Supplies
Serial Digital Interface Compatible with ADSP-21xx
Fixed-Point DSP
PRODUCT OVERVIEW
The AD1847 SoundPort® Stereo Codec integrates key audio
data conversion and control functions into a single integrated
circuit. The AD1847 is intended to provide a complete, low
cost, single-chip solution for business, game audio and multi-
media applications requiring operation from a single +5 V sup-
ply. It provides a serial interface for implementation on a
computer motherboard, add-in or PCMCIA card. See Figure 1
for an example system diagram.
*Windows Sound System is a registered trademark of Microsoft Corp.
SoundPort is a registered trademark of Analog Devices, Inc.
I
S
A
ASIC
B
U
S DSP
AD1847
Figure 1. Example System Diagram
External circuit requirements are limited to a minimal number
of low cost support components. Anti-imaging DAC output
filters are incorporated on-chip. Dynamic range exceeds 70 dB
over the 20 kHz audio band. Sample rates from 5.5 kHz to
48 kHz are supported from external crystals.
The Codec includes a stereo pair of ∑∆ analog-to-digital con-
verters (ADCs) and a stereo pair of ∑∆ digital-to-analog con-
verters (DACs). Inputs to the ADC can be selected from four
stereo pairs of analog signals: line 1, line 2, auxiliary (“aux”)
line #1, and post-mixed DAC output. A software-controlled
programmable gain stage allows independent gain for each
channel going into the ADC. The ADCs’ output can be digitally
mixed with the DACs’ input.
The pair of 16-bit outputs from the ADCs is available over a se-
rial interface that also supports 16-bit digital input to the DACs
and control/status information. The AD1847 can accept and
generate 16-bit twos-complement PCM linear digital data, 8-bit
unsigned magnitude PCM linear data, and 8-bit µ-law or A-law
companded digital data.
(Continued on page 7)
FUNCTIONAL BLOCK DIAGRAM
ANALOG ANALOG DIGITAL
I/O SUPPLY SUPPLY
LINE 1 L
INPUT R
LINE 2 L
INPUT R
AUX 1 L
INPUT R
ML
U
X
R
CLOCK
OUT
CRYSTALS
22
GAIN
GAIN
∑∆ A/D
CONVERTER
∑∆ A/D
CONVERTER
OSCILLATORS
µ/A
LAW
µ/A
LAW
L
LINE
OUTPUT
R
L
AUX 2
INPUT
R
GAIN/ATTEN/MUTE
ATTEN
L
∑
ATTEN/
∑∆ D/A
MUTE CONVERTER
ATTEN ∑
µ/A
LAW
R
∑
ATTEN/
∑∆ D/A
MUTE CONVERTER
ATTEN
∑
µ/A
LAW
GAIN/ATTEN
/MUTE
GAIN/ATTEN
/MUTE
REFERENCE
AD1847
S
E
R
I
A
L
P
O
R2
T
DIGITAL
I/O
RESET
POWER
DOWN
BUS
MASTER
TIME SLOT
INPUT
TIME SLOT
OUTPUT
SERIAL DATA
OUTPUT
SERIAL DATA
INPUT
EXTERNAL
CONTROL
SERIAL BIT
CLOCK
FRAME
SYNC
REV. B
2.25V
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
® Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD1847
ABSOLUTE MAXIMUM RATINGS*
Min Max
Units
Power Supplies
Digital (VDD)
Analog (VCC)
Input Current
–0.3
–0.3
(Except Supply Pins)
Analog Input Voltage (Signal Pins) –0.3
Digital Input Voltage (Signal Pins) –0.3
Ambient Temperature (Operating) 0
Storage Temperature
–65
6.0
6.0
± 10.0
(VA+) + 0.3
(VD+) + 0.3
+70
+150
V
V
mA
V
V
°C
°C
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
Temperature Package
Range
Description
AD1847JP 0°C to +70°C 44-Lead PLCC
AD1847JST 0°C to +70°C 44-Lead TQFP
*P = PLCC; ST = TQFP.
Package
Option*
P-44A
ST-44
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1847 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
44-Lead PLCC
PINOUTS
44-Lead TQFP
6 5 4 3 2 1 44 43 42 41 40
TSO 7
TSI 8
VDD 9
GNDD 10
RESET 11
PWRDOWN 12
VCC 13
GNDA 14
VREFI 15
VREF 16
R_LINE1 17
AD1847JP
Top View
(Not to Scale)
39 VDD
38 GNDD
37 XCTL1
36 XCTL0
35 GNDD
34 VDD
33 BM
32 L_AUX2
31 R_AUX2
30 L_OUT
29 N/C
18 19 20 21 22 23 24 25 26 27 28
N/C = NO CONNECT
TSO 1
TSI 2
VDD 3
GNDD 4
RESET 5
PWRDOWN 6
VCC 7
GNDA 8
VREFI 9
VREF 10
R_LINE1 11
PIN 1 IDENTIFIER
AD1847JST
Top View
(Not to Scale)
N/C = NO CONNECT
33 VDD
32 GNDD
31 XCTL1
30 XCTL0
29 GNDD
28 VDD
27 BM
26 L_AUX2
25 R_AUX2
24 L_OUT
23 N/C
REV. B
–5–
5 Page 
AD1847
Status Word (16-Bit)
Data 15
res
Data 7
res
Data 14
res
Data 6
res
Data 13
RREQ
Data 5
ORR1
Data 12
res
Data 4
ORR0
Data 11
ID3
Data 3
ORL1
Data 10
ID2
Data 2
ORL0
Data 9
ID1
Data 1
ACI
Data 8
ID0
Data 0
INIT
INIT
Initialization. This bit is an indication to the host that frame syncs will stop and the serial bus will be shut down. INIT is
set HI on the last valid frame. It is reset LO for all other frames. Read by the host CPU or DSP from the AD1847.
The INIT bit is set HI on the last sample before the serial interface is inactivated. The only condition under which the
INIT bit is set is when a different sample rate is programmed. If FRS = 0 (32 slots per frame, two samples per frame)
and the sample rate is changed in the first sample of the 32 slot frame (i.e., during slots 0 through 15), the INIT bit will
be set on the second sample of that frame (i.e., during slots 16 through 31). If FRS = 0 and the sample rate is changed in
the second sample of the 32 slot frame, the INIT bit will be set on the second sample of the following frame.
ACI Autocalibrate In-Progress. This bit indicates that autocalibration is in progress or the Mode Change Enable (MCE) state
has been recently exited. When exiting the MCE state with the ACAL bit set, the ACI bit will be set HI for 384 sample
periods. When exiting the MCE state with the ACAL bit reset, the ACAL bit will be set HI for 128 sample periods, indi-
cating that offset and filter values are being restored. Read by the host CPU or DSP from the AD1847.
0 Autocalibration not in progress
1 Autocalibration is in progress
ACI clear (i.e., reset or LO) should be recognized by first polling for a HI on the sample after the MCE bit is reset, and
then polling for a LO. Note that it is important not to start polling until one sample after MCE is reset, because if MCE
is set while ACI is HI, an ACI LO on the following sample will suggest a false clear of ACI.
ORL1:0 Overrange Left Detect. These bits indicate the overrange on the left input channel. Read by the host CPU or DSP from
the AD1847.
0 Greater than –1.0 dB underrange
1 Between –1.0 dB and 0 dB underrange
2 Between 0 dB and 1.0 dB overrange
3 Greater than 1.0 dB overrange
ORR1:0 Overrange Right Detect. These bits indicate the overrange on the right input channel. Read by the host CPU or DSP
from the AD1847.
0 Greater than –1.0 dB underrange
1 Between –1.0 dB and 0 dB underrange
2 Between 0 dB and 1.0 dB overrange
3 Greater than 1.0 dB overrange
ID3:0
AD1847 Revision ID. These four bits define the revision level of the AD1847. The first version of the AD1847 is desig-
nated ID = 0001. Read by the host CPU or DSP from the AD1847.
RREQ
This bit is reset LO for the Status Word, echoing the RREQ state written by the host CPU or DSP in the previous Con-
trol Word. Read by the host CPU or DSP from the AD1847.
res Reserved for future expansion. All reserved bits read zero (LO).
Immediately after reset, the contents of this register is: 0000 0001 0000 0000 (0100h).
REV. B
–11–
11 Page | ||
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| PDF Descargar | [ Datasheet AD1847.PDF ] | |
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