|
|
PDF AD1845 Data sheet ( Hoja de datos )
| Número de pieza | AD1845 | |
| Descripción | Parallel-Port 16-Bit SoundPort Stereo Codec | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD1845 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
a
Parallel-Port 16-Bit
SoundPort® Stereo Codec
AD1845
FEATURES
Single-Chip Integrated ∑∆ Digital Audio Stereo Codec
Microsoft® and Windows® Sound System Compatible
MPC Level-2+ Compliant Mixing
16 mA Bus Drive Capability
Supports Two DMA Channels for Full Duplex Operation
On-Chip Capture and Playback FIFOs
Advanced Power-Down Modes
Programmable Gain and Attenuation
Sample Rates from 4.0 kHz to 50 kHz Derived from a
Single Clock or Crystal Input
68-Lead PLCC, 100-Lead TQFP Packages
Operation from +5 V Supplies
Byte-Wide Parallel Interface to ISA and EISA Buses
Pin Compatible with AD1848, AD1846, CS4248, CS4231
PRODUCT OVERVIEW
The Parallel Port AD1845 SoundPort Stereo Codec integrates
key audio data conversion and control functions into a single
integrated circuit. The AD1845 provides a complete, single chip
computer audio solution for business audio and multimedia
applications. The codec includes stereo audio converters, com-
plete on-chip filtering, MPC Level-2 compliant analog mixing,
programmable gain, attenuation and mute, a variable sample
frequency generator, FIFOs, and supports advanced power-
down modes. It provides a direct, byte-wide interface to both
ISA (“AT”) and EISA computer buses for simplified implemen-
tation on a computer motherboard or add-in card.
The AD1845 SoundPort Stereo Codec supports a DMA re-
quest/grant architecture for transferring data with the host com-
puter bus. One or two DMA channels can be supported.
Programmed I/O (PIO) mode is also supported for control
register accesses and for applications lacking DMA control.
Two input control lines support mixed direct and indirect ad-
dressing of thirty-seven internal control registers over this asyn-
chronous interface. The AD1845 includes dual DMA count
registers for full duplex operation enabling the AD1845 to cap-
ture data on one DMA channel and play back data on a separate
channel. The FIFOs on the AD1845 reduce the risk of losing
data when making DMA transfers over the ISA/EISA bus. The
FIFOs buffer data transfers and allow for relaxed timing in
acknowledging requests for capture and playback data.
(Continued on Page 9)
FUNCTIONAL BLOCK DIAGRAM
ANALOG
ANALOG SUPPLY
DIGITAL SUPPLY
CLOCK SOURCE POWER DOWN
RESET
DIGITAL
L_MIC
R_MIC
L_LINE
R_LINE
L_AUX1
R_AUX1
L_OUT
M_OUT
R_OUT
M_IN
L_AUX2
R_AUX2
0 dB/
20 dB
VARIABLE SAMPLE
FREQUENCY GENERATOR
L
M
U
XR
GAIN
GAIN
⌺⌬ A/D
CONVERTER
⌺⌬ A/D
CONVERTER
AD1845
-LAW
A-LAW
LINEAR
FIFO
MUTE
GAM
⌺
⌺
⌺
GAM
⌺
⌺
GAM
⌺
GAM = GAIN
ATTENTUATE
MUTE
DIGITAL MIX
ATTENUATE
L ATTENUATE
MUTE
⌺⌬ D/A
CONVERTER
⌺
R
⌺
ATTENUATE
MUTE
⌺⌬ D/A
CONVERTER
⌺
-LAW
A-LAW
LINEAR
GAM
GAM
FIFO
P
A
R
A
L
L
E
L
P
O
R
T
PLAYBACK REQ
PLAYBACK ACK
CAPTURE REQ
CAPTURE ACK
ADR1:0
DATA7:0
CS
RD
WR
BUS DRIVER
CONTROL
HOST DMA
INTERRUPT
EXTERNAL
CONTROL
REFERENCE
CONTROL
REGISTERS
SoundPort is a registered trademark of Analog Devices, Inc.
Microsoft and Windows are registered trademarks of Microsoft Corporation.
VREF_F VREF
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1997
1 page  
POWER SUPPLY
Power Supply Range–Digital and Analog
Power Supply Current
Analog Supply Current
Digital Supply Current
Power Dissipation
(Current × Nominal Supplies)
Power-Down Supply Current
Reset Supply Current
Total Power-Down Supply Current
Standby Supply Current
Mixer Power-Down Supply Current
Mixer Only Supply Current
ADC Power-Down Supply Current
DAC Power-Down Supply Current
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)*
(At Both Analog and Digital Supply Pins, both ADCs and DACs)
AD1845
Min Typ
4.75
2
36
52
40
Max Units
5.25 V
130 mA
45 mA
85 mA
650 mW
2 mA
mA
30 mA
mA
70 mA
mA
80 mA
85 mA
dB
CLOCK SPECIFICATIONS*
Input Clock Frequency
Recommended Clock Duty Cycle
Power Up Initialization Time
*Guaranteed, not tested.
Specifications subject to change without notice.
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option1
AD1845JP
AD1845JP-REEL2
AD1845JST
0°C to +70°C
0°C to +70°C
0°C to +70°C
68-Lead PLCC P-68A
68-Lead PLCC P-68A
100-Lead TQFP ST-100
NOTES
1P = Plastic Leaded Chip Carrier; ST = Thin Quad Flatpack.
213" Reel, multiples of 250 pcs.
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating:
TAMB = TCASE – (PD × θCA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
θCA = Thermal Resistance (Case-to-Ambient)
θJA = Thermal Resistance (Junction-to-Ambient)
θJC = Thermal Resistance (Junction-to-Case)
Package
PLCC
TQFP
JA
38°C/W
44°C/W
JC
8°C/W
8°C/W
CA
30°C/W
93°C/W
Min Max Units
33 MHz
10 90 %
512 ms
ABSOLUTE MAXIMUM RATINGS*
Min Max
Units
Power Supplies
Digital (VDD)
Analog (VCC)
Input Current
(Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Ambient Temperature (Operating)
Storage Temperature
–0.3
–0.3
–0.3
–0.3
0
–65
6.0
6.0
± 10.0
VCC +0.3
VDD +0.3
+70
+150
V
V
mA
V
V
°C
°C
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1845 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. C
–5–
WARNING!
ESD SENSITIVE DEVICE
5 Page 
AD1845
15
COMPRESSED
INPUT DATA
MSB
15
EXPANSION MSB
87
LSB
0
3/2 2/1
LSB
0
15
DAC INPUT MSB
3/2 2/1
0
LSB 0 0 0 / 0 0
Figure 2. µ-Law or A-Law Expansion
When 8-bit companding is specified, the ADCs’ linear output is
compressed to the format specified.
15
ADC OUTPUT MSB
0
LSB
15
TRUNCATION MSB
3/2 2/1
LSB
0
15
COMPRESSION MSB
87
LSB
00000000
0
Figure 3. µ-Law or A-Law Compression
Note that all format conversions take place at input or output.
Internally, the AD1845 always uses 16-bit linear PCM represen-
tations to maintain maximum precision.
Timer Registers
The timer registers are provided for system level synchroniza-
tion, and for periodic interrupt generation. The 16-bit timer
time base is determined by the frequency of the connected input
clock source.
The timer is enabled by setting the Timer Enable bit, TE, in the
Alternate Feature Enable register. To set the timer, load the
Upper and Lower Timer Bits Registers. The timer value will
then be loaded into an internal count register with a value of
approximately 10 µs (the exact timer value is listed in the regis-
ter descriptions). The internal count register will decrement
until it reaches zero, then the Timer Interrupt bit, TI, is set and
an interrupt will be sent to the host. The next timer clock will
load the internal count register with the value of the Timer
Register, and the timer will be reinitialized. To clear the inter-
rupt, write to the Status Register or write a “0” to TI.
Interrupts
The AD1845 supports interrupt conditions generated by DMA
playback count expiration, DMA capture count expiration, or
timer expiration. The INT bit will remain set, HI, until a write
has been completed to the Status Register or by clearing the TI,
CI, or PI bit (depending on the existing condition) in the Cap-
ture Playback Timer Register. The IEN bit of the Pin Control
Register determines whether the interrupt pin responds to an
interrupt condition and reflects the interrupt state on the
INT status bit.
Power Supplies and Voltage Reference
The AD1845 operates from a +5 V power supply. Independent
analog and digital supplies are recommended for optimal perfor-
mance though excellent results can be obtained in single-supply
systems. A voltage reference is included on the codec and its
2.25 V buffered output is available on an external pin (VREF).
The reference output can be used for biasing op amps used in
dc coupling. The internal reference is externally bypassed to
analog ground at the VREF_F pin.
Clocks and Sample Rates
The AD1845 operates from a single external crystal or clock
source. From a single input, a wide range of sample rates can be
generated. The AD1845 default frequency source is a
24.576 MHz input. The AD1845 can also be driven from a
14.31818 MHz (OSC), 24 MHz, 25 MHz or 33 MHz input
frequency source. In MODE1, the input drives the internal
variable sample frequency generator to derive the following
AD1848 compatible sample rates: 5.5125, 6.615, 8, 9.6,
11.025, 16, 18.9, 22.05, 27.42857, 32, 33.075, 37.8, 44.1,
48 kHz. In MODE2, the AD1845 can be programmed to gen-
erate any sample frequency between 4 kHz and 50 kHz with
1 Hz resolution. Note that it is no longer required to enter
Mode Change Enable (MCE) to change the sample rate. This
feature allows the user to change the AD1845’s sample rate “on
the fly.”
CONTROL REGISTERS
Control Register Architecture
The AD1845 SoundPort Stereo Codec accepts both data and
control information through its byte-wide parallel port. Indirect
addressing minimizes the number of external pins required to
access all 37 of its byte-wide internal registers. Only two exter-
nal address pins, ADR1:0, are required to accomplish all data
and control transfers. These pins select one of five direct regis-
ters. (ADR1:0 = 3 addresses two registers, depending on
whether the transfer is for a playback or capture.)
ADR1:0 Register Name
0 Index Address Register
1 Indexed Data Register
2 Status Register
3 PIO Data Register
Figure 4. Direct Register Map
REV. C
–11–
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD1845.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD1843 | Serial-Port 16-Bit SoundComm Codec | Analog Devices |
| AD1845 | Parallel-Port 16-Bit SoundPort Stereo Codec | Analog Devices |
| AD1846 | Low Cost Parallel-Port 16-Bit SoundPort Stereo Codec | Analog Devices |
| AD1847 | Serial-Port 16-Bit SoundPort Stereo Codec | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |